Abstract: A semiconductor device includes a chip and an electrode that has a laminated structure including a Ti film, a TiN film, a TiAl alloy film and an Al-based metal film that are laminated in that order from the chip side.

Abstract: An SiC semiconductor device includes an SiC chip having a first main surface at one side and a second main surface at another side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and to be connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface.

Abstract: Methods and systems are disclosed for increased speed of processing operations on data in two-dimensional arrays, and for detecting a feature in an image. A method for detecting a feature in an image comprises storing, in a set of data memories within a parallel processing system, first image data representing pixels of a first image. The method further comprises storing, in a memory of a host processor coupled to the parallel processing system, feature kernel data representing a set of weight matrices. A method for increased speed of processing operations on data in two-dimensional arrays comprises storing, in a set of data memories within a parallel processing system, first array data representing elements of a first array. The method further comprises, for each of multiple selected elements within the first array, performing a processing operation on the selected element to produce an output element corresponding to the selected element.

Abstract: Methods and systems are disclosed for increased speed of processing operations on data in two-dimensional arrays, and for detecting a feature in an image. A method for detecting a feature in an image comprises storing, in a set of data memories within a parallel processing system, first image data representing pixels of a first image. The method further comprises storing, in a memory of a host processor coupled to the parallel processing system, feature kernel data representing a set of weight matrices. A method for increased speed of processing operations on data in two-dimensional arrays comprises storing, in a set of data memories within a parallel processing system, first array data representing elements of a first array. The method further comprises, for each of multiple selected elements within the first array, performing a processing operation on the selected element to produce an output element corresponding to the selected element.

Abstract: Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.

Abstract: A method of manufacturing an outer retainer for a one-way clutch having an outward flange at one side edge thereof involves punching out a part of an annular portion having the outward flange by sliding a punch toward an axis of the outer retainer substantially in an axially inner direction from a retainer outer periphery-sided curve portion of the outward flange to a retainer inner periphery-sided curve portion thereof in a way that uses a die and the punch.

Abstract: Methods and apparatus to facilitate improve code division multiple access (CDMA) receivers are disclosed. An example method disclosed herein comprises: receiving a signal containing first portions that are based on known data and second portions that are based on unknown data; generating a training signal, from the received signal, that substantially represents one or more of the first portions; adapting filter coefficients using the training signal; and equalizing the received signal using the adapted filter coefficients.

Abstract: A method of producing a semiconductor device includes the steps of preparing an SOQ (Silicon On Quartz) substrate in which a semiconductor layer is formed on a quartz substrate; forming a plurality of semiconductor device forming regions in the SOQ substrate; forming a crack inspection pattern in the SOQ substrate; inspecting the crack inspection pattern to detect a crack in the crack inspection pattern in a first inspection step; and inspecting the semiconductor device forming regions to detect a crack in the semiconductor device forming regions in a second inspection step when the crack is detected in the crack inspection pattern in the first inspection step.

Abstract: Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system in provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user.

Abstract: Methods and apparatus to perform frequency-domain equalization in high-speed downlink packet access (HSDPA) receivers for wireless channels with large delay-spreads are disclosed. An example method comprises computing a first frequency-domain equalizer (FDE) coefficient for a first set of multipaths, computing a second FDE coefficient for a second set of multipaths, computing a first equalized signal by equalizing a received code division multiple access (CDMA) signal with the first FDE coefficient, computing a second equalized signal by equalizing the received CDMA signal with the second FDE coefficient, delaying the first equalized signal by a delay difference between the first and the second sets, and combining the delayed first equalized signal and the second equalized signal.

Abstract: A method of producing a semiconductor device includes the steps of preparing an SOQ (Silicon On Quartz) substrate in which a semiconductor layer is formed on a quartz substrate; forming a plurality of semiconductor device forming regions in the SOQ substrate; forming a crack inspection pattern in the SOQ substrate; inspecting the crack inspection pattern to detect a crack in the crack inspection pattern in a first inspection step; and inspecting the semiconductor device forming regions to detect a crack in the semiconductor device forming regions in a second inspection step when the crack is detected in the crack inspection pattern in the first inspection step.

Abstract: A method of manufacturing an outer retainer for a one-way clutch having an outward flange at one side edge thereof involves punching out a part of an annular portion having the outward flange by sliding a punch toward an axis of the outer retainer substantially in an axially inner direction from a retainer outer periphery-sided curve portion of the outward flange to a retainer inner periphery-sided curve portion thereof in a way that uses a die and the punch.

Abstract: In a first embodiment, Tetraethyl Orthosilicate Si(OC2H5)4 is used at the process temperature of 650° C.±5° C. as film forming material, to decrease crystal defects occurring during deposition. In a second embodiment, annealing is carried out in sparse oxygen gas atmosphere after deposition, to mend crystal defects that occurred during deposition. In a third embodiment, initial temperature of the CVD device is kept at about 400° C., whereby the start of natural oxidation of the deposition surface is prevented and production circumstances of the semiconductor element is not deteriorated. Then, the CVD device is heated up to CVD temperature of about 750° C. or about 650° C., to deposit oxide.

Abstract: According to the present invention, a method for fabricating a semiconductor device using a Silicon-On-Sapphire (SOS) wafer comprises a process for preparing a sapphire substrate, a process for forming a silicon (Si) layer on the sapphire substrate, a process for implanting silicon ions in the silicon layer, and a process for inducing epitaxial regrowth in the silicon layer after the silicon ion implantation. The silicon ion implantation process induces the number of interstitial Si having crystalline defects in the proximity of the surface of said silicon layer to be reduced below 6.5E2/cm3; and induces an ion implantation amount per unit area of said silicon ions in the proximity of an interface between said sapphire substrate and said silicon layer to be increased to 3.0E19 ions/cm3 or more.

Abstract: Methods and apparatus to perform frequency-domain equalization in high-speed downlink packet access (HSDPA) receivers for wireless channels with large delay-spreads are disclosed. An example method comprises computing a first frequency-domain equalizer (FDE) coefficient for a first set of multipaths, computing a second FDE coefficient for a second set of multipaths, computing a first equalized signal by equalizing a received code division multiple access (CDMA) signal with the first FDE coefficient, computing a second equalized signal by equalizing the received CDMA signal with the second FDE coefficient, delaying the first equalized signal by a delay difference between the first and the second sets, and combining the delayed first equalized signal and the second equalized signal.

Abstract: Methods and apparatus to perform noise estimation for frequency-domain equalizers of high-speed downlink packet access (HSDPA) receivers are disclosed. An example method comprises measuring a total power associated with a code division multiple access (CDMA) signal received through a plurality of multipaths, measuring a plurality of channel responses for respective ones of the plurality of multipaths, measuring a plurality of noise plus inter-path interference powers for the respective ones of the plurality of multipaths, and estimating an additive noise power for the received CDMA signal based on the total power, the plurality of channel responses and the plurality of noise plus inter-path interference powers.

Abstract: Methods and apparatus to perform closed-loop transmit diversity with frequency-domain equalizers in high-speed downlink packet access (HSDPA) receivers are disclosed. An example method comprises receiving a first signal representative of a first code division multiple access (CDMA) signal received from a first transmit antenna and a second signal representative of a second CDMA signal received from a second transmit antenna, computing a first channel estimate for a first path from the first transmit antenna to the receiver, computing a second channel estimate for a second path from the second transmit antenna to the receiver, and computing a frequency-domain equalizer (FDE) coefficient for the first path based on the first and the second channel estimates.

Abstract: Methods and apparatus to perform fractional-spaced channel estimation for frequency-domain equalizers in high-speed downlink packet access (HSDPA) receivers are disclosed. An example method comprises computing a first fractionally-spaced time-domain channel estimate from an oversampled CDMA signal, and computing a first chip-interval frequency-domain equalizer (FDE) coefficient from the first fractionally-spaced channel estimate.

Abstract: In a first embodiment, Tetraethyl Orthosilicate Si(OC2H5)4 is used at the process temperature of 650° C.±5° C. as film forming material, to decrease crystal defects occurring during deposition. In a second embodiment, annealing is carried out in sparse oxygen gas atmosphere after deposition, to mend crystal defects that occurred during deposition. In a third embodiment, initial temperature of the CVD device is kept at about 400° C., whereby the start of natural oxidation of the deposition surface is prevented and production circumstances of the semiconductor element is not deteriorated. Then, the CVD device is heated up to CVD temperature of about 750° C. or about 650° C., to deposit oxide.

Abstract: A newly discovered, and asexually prorogated genotype of Centipedegrass with a distinct set of agronomic, horticultural, and morphological traits.