Abstract: A semiconductor substrate has a main surface oriented to {1 1 1} face, a first orientation flat formed on a peripheral portion of a semiconductor substrate and oriented to one of {1 1 1} face and {1 1 2} face perpendicular to the {1 1 0} face. It is easy to select (determine) {1 1 1} face for forming a trench in the semiconductor substrate based on the first orientation flat. In addition, the trench whose face is oriented to {1 1 1} face has few defects on its inner surface.

Abstract: In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

Abstract: In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

Abstract: A trench is formed in a silicon substrate, and an epitaxial film is formed on the substrate and in the trench. After a part of the epitaxial film formed around an opening portion of the trench is etched, another epitaxial film is formed on the substrate and in the trench. Accordingly, the trench can be filled with the epitaxial films completely. Then, the surface of the substrate is flattened.

Abstract: An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.

Abstract: A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.

Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

Abstract: The door stopper of the present invention is of a construction such that a door contacting member fitted into a guide cylinder sunk vertically into the floor is allowed to be set in two positions, in a door contacting state in which it protrudes from the floor and in a housed state in which the top is substantially level with the floor. According to this construction, the floor is able to be substantially flat when the door stopper is not in use so that it does not become an obstruction to floor polishers and wheelchairs.

Abstract: A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.

Abstract: A semiconductor substrate has a main surface oriented to {1 1 0} face, a first orientation flat formed on a peripheral portion of a semiconductor substrate and oriented to one of {1 1 1} face and {1 1 2} face perpendicular to the {1 1 0} face. It is easy to select (determine) {1 1 1} face for forming a trench in the semiconductor substrate based on the first orientation flat. In addition, the trench whose face is oriented to {1 1 1} face has few defects on its inner surface.

Abstract: An island region surrounded by a trench is provided in an SOI substrate. The island region is further surrounded by a buffer region with a buffer region contact layer. In the island region, a source region is annularly provided around a drain region, and source and drain electrodes are respectively provided on the source and the drain regions. An annular auxiliary electrode is formed with the source electrode to extend over the trench. Accordingly, a voltage applied to the source electrode can be applied to the auxiliary electrode, so that electric field concentration between the buffer region and the source electrode is relaxed.

Abstract: A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.

Abstract: A semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. A PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14.

Abstract: A trench isolation junction type SOI semiconductor device which reduces substrate warpage while suppressing increase in production steps and a method for producing the same are disclosed. A junction substrate is formed by bonding a semiconductor substrate having an outer insulation film on a non-junction main surface with a semiconductor layer with an inner insulation film sandwiched therebetween. After forming a silicon nitride film as a mask for the purpose of forming a trench in the semiconductor layer, silicon nitride film accumulated on the outer insulation film is removed. By doing this, warpage of the semiconductor substrate due to discrepancies in the thermal expansion rates of the rigid silicon nitride film and semiconductor substrate can be prevented. In a junction type SOI semiconductor device formed via the method, an outer insulation film of identical thickness and identical density to an inner insulation film is formed on a non-junction main surface (i.e.

Abstract: A semiconductor device is provided which makes a high withstand voltage bipolar transistor small and prevents deterioration in a switching speed of the transistor. A silicon oxide layer is formed on a silicon substrate, and a semiconductor island of one conductivity type which is isolated laterally by an isolation trench is formed on the silicon oxide layer. A silicon oxide film is formed on an outer periphery portion of the semiconductor island to bury the trench. In the semiconductor island, a bipolar transistor, namely a base region of the other conductivity type, is formed, and in the base region an emitter region of one conductivity type is formed and a collector region of one conductivity type is further formed. In the semiconductor island a diffusion region of the other conductivity type for extracting excessive carriers to which a constant electric potential is applied is further formed.

Abstract: A dielectric isolated type semiconductor device which can achieve a reduction in crystalline defects by means of a simple production process is provided. High-concentration regions are formed as active regions on a surface portion of an islandish semiconductor region which is isolated from an adjacent semiconductor region by means of an isolation trench. According to a first aspect of the present invention, an N type crystalline defect suppression region doped at a high concentration and deeper than the high-concentration regions is formed over the entire surface of an adjacent semiconductor region. According to a second aspect of the present invention, a high-concentration N type crystalline defect suppression region is provided on a surface portion of a P type high-concentration region is formed with identical structure and by an identical production process. By means of these N type regions, crystalline defects are reduced.

Abstract: An object of the invention is to prevent the occurrence of breaking or short-circuiting of a wiring caused by a difference in level in an isolation trench area formed in an SOI substrate. An oxide film is formed for a pad on the main surface of an SOI layer formed on an insulating substrate, a silicon nitride film are formed and an SiO.sub.2 film in order, then an isolation trench reaching to the insulating substrate is by means of an R.I.E process using the SiO.sub.2 film as a mask. Thereafter an insulating film is formed on an inside wall of the isolation trench by means of thermal oxidation, the isolation trench is filled with polysilicon, the polysilicon is etched back while controlling the etching so that the top of the polysilicon in the isolation trench remains higher than the top of the silicon nitride film, an extra part of the polysilicon deposited on the surface of the substrate, is removed and then the SiO.sub.

Abstract: A semiconductor device is provided in which a contact is very simply formed on conductive material for capacitive coupling prevention. Two silicon substrates are bonded through a silicon oxide film. And a trench extending to the silicon oxide film is formed in one of silicon substrates so as to isolate between plural circuit elements from each other, and islands for circuit element formation are compartmently formed by the trench. A silicon oxide film is formed on an outer periphery portion of the islands for circuit element formation. Furthermore, an island for capacitive coupling prevention is formed by the silicon substrate between the islands for circuit element formation and is applied thereto to be maintained in an electric potential of constant.

Abstract: A semiconductor device is provided which comprises a single crystalline substrate having a main surface, an insulating layer formed on the main surface of the single crystalline substrate, and a semiconductor region of a single crystal formed on the insulating layer, wherein the semiconductor region has top and bottom surfaces and a thickness of not more than 6 .mu.m and an impurity is doped in the semiconductor region from the top to bottom surfaces thereof, a concentration of the impurity gradually decreasing from the top to bottom surfaces, whereby the semiconductor region is made a first conductivity type by the doped impurity. The semiconductor device further comprises an insulating gate type field effect transistor including source and drain regions in the semiconductor region, the source and drain regions having a conductive type opposite to that of the first conductivity type, and further there is provided a process for manufacturing such a semiconductor device.

Abstract: A first polysilicon film serving as an erase gate is deposited on the major surface of a semiconductor substrate on which a field oxide film is formed, so that the surface of the first polysilicon film is roughened. The surface of the first polysilicon film is thermally oxidized to form a first thermal oxide film thereon. During the oxidation, the roughened surface of the first polysilicon film is flattened, and is duplicated by the surface of the first thermal oxide film. A second polysilicon film is deposited on the roughened surface of the first thermal oxide film. The back surface of the second polysilicon film is roughened by the roughened surface of the first thermal oxide film. In this case, the surface of the second polysilicon film is also roughened. The roughened surface of the second polysilicon film is thermally oxidized in the same manner as described above to flatten its surface and to form a second thermal oxide film, the surface of which is roughened.