Patents by Inventor Toshio Sakakibara

Toshio Sakakibara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4774556
    Abstract: A non-volatile semiconductor memory device comprises a semiconductor substrate of a first conduction type, an impurity buried layer of a second conduction type formed at the surface of the semiconductor substrate for constituting either one of a drain region or a source region, an epitaxial layer of a second conduction type formed at the surface of said impurity buried layer, an insulatiang partition wall extended vertically from the surface of the epitaxial layer surrounding operation regions in the impurity buried layer for defining the operation regions therein, at least one electron holding portion extended vertically with a predetermined distance from the operation regions and disposed within the insulating partition wall apart from the operation region, the impurity buried layer or the drain region by an insulation film of such a thickness as causing a tunnel effect, control gates disposed within the insulation partition wall disposed on every electron holding portions on the side opposite to the operat
    Type: Grant
    Filed: July 21, 1986
    Date of Patent: September 27, 1988
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tetsuo Fujii, Nobuyoshi Sakakibara, Toshio Sakakibara, Hiroshi Iwasaki