Patents by Inventor Toshio Sugano
Toshio Sugano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080164058Abstract: A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring are arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.Type: ApplicationFiled: December 20, 2007Publication date: July 10, 2008Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
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Publication number: 20080123303Abstract: A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.Type: ApplicationFiled: November 27, 2007Publication date: May 29, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Toshio Sugano, Shunichi Saito, Atsushi Hiraishi
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Publication number: 20080111582Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.Type: ApplicationFiled: December 31, 2007Publication date: May 15, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda
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Patent number: 7327590Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.Type: GrantFiled: July 26, 2006Date of Patent: February 5, 2008Assignee: Elpida Memory, Inc.Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda
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Publication number: 20070273021Abstract: A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.Type: ApplicationFiled: May 25, 2007Publication date: November 29, 2007Inventors: Fumiyuki Osanai, Atsushi Hiraishi, Toshio Sugano, Tsuyoshi Tomoyama, Satoshi Isa, Masahiro Yamaguchi, Masanori Shibamoto
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Patent number: 7227251Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.Type: GrantFiled: April 26, 2005Date of Patent: June 5, 2007Assignee: Elpida Memory, Inc.Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
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Publication number: 20070001299Abstract: A stacked semiconductor package comprises two semiconductor chips (11, 12) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate (13) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.Type: ApplicationFiled: September 12, 2006Publication date: January 4, 2007Applicant: ELPIDA MEMORY, INC.Inventors: Wataru KIKUCHI, Toshio SUGANO, Satoshi ISA
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Publication number: 20060262587Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.Type: ApplicationFiled: July 26, 2006Publication date: November 23, 2006Applicant: ELPIDA MEMORY, INC.Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda
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Patent number: 7123497Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, it has become clear that there is a restriction on the transfer rate of the system data signal and that speeding-up cannot be expected. A current consumption in a plurality of DRAMs constituting the memory module is large, and this is also a factor for hindering the speeding-up. There is obtained a memory module in which a plurality of DRAM chips are stacked on an IO chip and in which each DRAM chip is connected to the IO chip by a through electrode and which comprises a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip.Type: GrantFiled: April 21, 2004Date of Patent: October 17, 2006Assignee: Elpida Memory, Inc.Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda
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Patent number: 7122883Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.Type: GrantFiled: December 3, 2004Date of Patent: October 17, 2006Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
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Patent number: 7102221Abstract: The invention is intended to increase the density for mounting the semiconductor chips on a memory-module, to increase the capacity of the memory-module, and to realize the memory-module capable of coping with high-speed buses. The memory-module comprises a plurality of WPPs having protruded terminals as external terminals and wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips, TSOPs having semiconductor chips, outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips, and a module board supporting the WPPs and the TSOPs, wherein the WPPs and the TSOPs are mounted by the simultaneous reflowing in a mixed manner on the module board.Type: GrantFiled: December 23, 2002Date of Patent: September 5, 2006Assignee: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Toshio Sugano
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Patent number: 7012321Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.Type: GrantFiled: March 4, 2003Date of Patent: March 14, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
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Register capable of corresponding to wide frequency band and signal generating method using the same
Patent number: 6986072Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.Type: GrantFiled: July 29, 2002Date of Patent: January 10, 2006Assignees: Elpida Memory, Inc., Hitachi Tohbu Semiconductor, Ltd., Hitachi, Ltd.Inventors: Yoji Nishio, Seiji Funaba, Kayoko Shibata, Toshio Sugano, Hiroaki Ikeda, Takuo Iizuka, Masayuki Sorimachi -
Patent number: 6978328Abstract: A bus system for carrying out data transfer between one bus master and a plurality of bus slaves. The bus system includes plural directional couplers which are formed by arranging respective parts of lines drawn from the bus slaves, without being in contact with, in the neighborhood of, and in parallel with a line drawn from the bus master. The line drawn from the bus master to a terminating resistance is wired to be folded. The directional couplers are further formed by arranging parts of the lines drawn from the bus slaves alternatively with respect to a first line part of the line drawn from the bus master ranging from the bus master to a fold of the line drawn from the bus master and with respect to a second line part of the line drawn from the bus master ranging from the fold to the terminating resistance.Type: GrantFiled: May 12, 2000Date of Patent: December 20, 2005Assignee: Hitachi, Ltd.Inventors: Hideki Osaka, Takashi Tsunehiro, Koichi Kimura, Susumu Hatano, Kazuya Ito, Toshio Sugano, Toyohiko Komatsu
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Publication number: 20050184380Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.Type: ApplicationFiled: April 26, 2005Publication date: August 25, 2005Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
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Publication number: 20050094433Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.Type: ApplicationFiled: December 3, 2004Publication date: May 5, 2005Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
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Publication number: 20050091440Abstract: To increase data transfer rate of a memory system in which a plurality of memory modules are stacked using mezzanine connectors, stacked blind vias and buried vias for connecting only specific layers are used as vias in a multilayer circuit board serving as a memory module board, and at least some of pads for mounting devices have a pad-on-via structure. Thus, the vias have no redundant portions which are not required for signal transmission and the length of surface-layer wiring can be remarkably reduced.Type: ApplicationFiled: October 26, 2004Publication date: April 28, 2005Inventors: Satoshi Isa, Toshio Sugano, Wataru Kikuchi
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Patent number: 6885092Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.Type: GrantFiled: December 2, 1999Date of Patent: April 26, 2005Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
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Publication number: 20040257847Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, it has become clear that there is a restriction on the transfer rate of the system data signal and that speeding-up cannot be expected. A current consumption in a plurality of DRAMs constituting the memory module is large, and this is also a factor for hindering the speeding-up. There is obtained a memory module in which a plurality of DRAM chips are stacked on an IO chip and in which each DRAM chip is connected to the IO chip by a through electrode and which comprises a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip.Type: ApplicationFiled: April 21, 2004Publication date: December 23, 2004Inventors: Yoshinori Matsui, Toshio Sugano, Hiroaki Ikeda
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Publication number: 20040227222Abstract: A stacked semiconductor package comprises two semiconductor chips (11, 12) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate (13) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.Type: ApplicationFiled: February 27, 2004Publication date: November 18, 2004Applicant: ELPIDA MEMORY, INCInventors: Wataru Kikuchi, Toshio Sugano, Satoshi Isa