Abstract: A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

Abstract: A memory TCP loaded with four chips (1-bank 16-bit type) is constructed by a tape of one two-layer wiring layer structure, four chips mounted to this tape, etc. Common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side. The common signal terminals on the two sides are electrically connected to each other common signal wiring. Further, in a DIMM in which this memory TCP is mounted to front and rear sides of a substrate, plural external terminals are formed on one long side of the rectangular substrate, and the memory TCP is mounted such that the independent signal terminal of the memory TCP is arranged along an arranging direction of these external terminals.

Abstract: A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

Abstract: First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

Abstract: Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: The invention is intended to increase the density for mounting the semiconductor chips on a memory-module, to increase the capacity of the memory-module, and to realize the memory-module capable of coping with high-speed buses. The memory-module comprises a plurality of WPPs having protruded terminals as external terminals and wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips, TSOPs having semiconductor chips, outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips, and a module board supporting the WPPs and the TSOPs, wherein the WPPs and the TSOPs are mounted by the simultaneous reflowing in a mixed manner on the module board.

Abstract: The invention is intended to increase the density for mounting the semiconductor chips on a memory-module, to increase the capacity of the memory-module, and to realize the memory-module capable of coping with high-speed buses. The memory-module comprises a plurality of WPPs having protruded terminals as external terminals and wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips, /TSOPs having semiconductor chips, outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips, and a module board supporting the WPPs and the TSOPs, wherein the WPPs and the TSOPs are mounted by the simultaneous reflowing in a mixed manner on the module board.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of 1/2 of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of singals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

Abstract: Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Abstract: A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.

Abstract: Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.

Abstract: A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips 1 are mounted on a substrate 2 in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips 1 are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate 2.