Patents by Inventor Toshio Yoshida

Toshio Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210302805
    Abstract: An O-ring seals between a first lens and a lens barrel. Further, between the second lens and the lens barrel is also sealed by a first adhesive layer. The lens barrel, in a state before manufacturing of the lens unit, is provided with a communication passage that communicates an inside of the lens barrel with an outer peripheral groove (outside of the lens barrel. The communication passage, in the state of FIG. 1 after manufacturing, is sealed by a second adhesive layer (third seal member) made of an adhesive.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 30, 2021
    Applicant: NIDEC SANKYO CORPORATION
    Inventors: Toshiyuki YOSHIDA, Toshio SHIROTORI
  • Patent number: 10884738
    Abstract: A Load and Store Queue (LDSTQ) stores load store instructions therein with an upper limit being a first number, and sequentially outputs the stored load store instructions to cause a data cache or a main memory to execute processing of data in accordance with the output load store instructions. A decode unit acquires load store instructions, and determines a queued number of load store instructions which have not been output from the LDSTQ among load store instructions output from the decode unit. When the queued number is smaller than a second number which is larger than the first number, the decode unit outputs the acquired load store instructions. An LDSTQ management unit acquires the output load store instructions. When the stored number of load store instructions stored in the LDSTQ is smaller than the first number, the LDSTQ management unit stores the acquired load store instructions in the LDSTQ.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: January 5, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Sota Sakashita, Toshio Yoshida
  • Patent number: 10831482
    Abstract: An arithmetic processing apparatus includes a decoder, a first cache memory, a second cache memory and a processor. The processor performs a cache hit determination on the first cache memory in response to a memory access instruction, issues a data request to a second cache memory when the cache hit determination is a cache miss. When the memory access instruction is for a speculative execution speculatively executed in a state where a branch destination of a branch instruction is unestablished, the decoder issues the memory access instruction with a valid prohibition flag and an instruction identifier. In a case where the cache hit determination is the cache miss and the prohibition flag is valid, the processor does not issue the data request to the second cache memory. In a case where the cache hit determination is a cache hit, the processor acquires data from the first cache memory.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 10, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yasunobu Akizuki, Toshio Yoshida
  • Publication number: 20200249196
    Abstract: In an ion concentration sensor, both an improvement of an SN ratio of output and high responsiveness are achieved. In an ion sensor (100), a sensing unit (1) accumulates as electron injected from an n-type substrate (21) via a p-well (22) as a signal charge. The p-well (22) is laminated on the n-type substrate (21). A concentration distribution of impurities exists in the p-well (22) located between the sensing unit (1) and the n-type substrate (21), and a maximum value C1 of an impurity concentration in the p-well (22) is 0<C1?3.0×1014 cm3.
    Type: Application
    Filed: October 4, 2016
    Publication date: August 6, 2020
    Applicants: SHARP KABUSHIKI KAISHA, SHARP KABUSHIKI KAISHA
    Inventors: YUKI EDO, YUKIO TAMAI, SHINOBU YAMAZAKI, TOSHIO YOSHIDA, YOSHIMITSU NAKASHIMA
  • Publication number: 20190377576
    Abstract: An arithmetic processing apparatus includes a decoder, a first cache memory, a second cache memory and a processor. The processor performs a cache hit determination on the first cache memory in response to a memory access instruction, issues a data request to a second cache memory when the cache hit determination is a cache miss. When the memory access instruction is for a speculative execution speculatively executed in a state where a branch destination of a branch instruction is unestablished, the decoder issues the memory access instruction with a valid prohibition flag and an instruction identifier. In a case where the cache hit determination is the cache miss and the prohibition flag is valid, the processor does not issue the data request to the second cache memory. In a case where the cache hit determination is a cache hit, the processor acquires data from the first cache memory.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 12, 2019
    Applicant: FUJITSU LIMITED
    Inventors: YASUNOBU AKIZUKI, Toshio Yoshida
  • Patent number: 10348990
    Abstract: A light detecting device includes: an optical filter (2) that transmits a first wavelength light having a wavelength in a first wavelength range, a second wavelength light having a wavelength in a second wavelength range, . . . , and an n-th wavelength light having a wavelength in an n-th wavelength range (n is an integer); an optical sensor (3) that detects at least one of a first wavelength light intensity of the first wavelength light, a second wavelength light intensity of the second wavelength light, . . . , and an n-th wavelength light intensity of the n-th wavelength light; and an analysis unit (4) that estimates a light intensity of light having a wavelength in a wavelength range other than at least one of the first wavelength range, the second wavelength range, . . . , and the n-th wavelength range based on at least one of the first wavelength light intensity, the second wavelength light intensity, . . . , and the n-th wavelength light intensity.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: July 9, 2019
    Assignees: SHARP KABUSHIKI KAISHA, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Toshihisa Gotoh, Toshio Yoshida, Yoshinobu Kanazawa, Yoshimitsu Nakashima, Kohji Kobayashi, Toshio Fukai, Hitoshi Aoki, Yasushi Nagamune, Takashi Tokizaki, Toshitaka Ota
  • Publication number: 20180368300
    Abstract: A new and distinct variety of Citrus L. plant named ‘ASUKI’, characterized by being late-maturing, having high brix and excellent taste, being easy to eat because of its soft segment membrane, having no occurrence of fruit rind puffing, and having less dripping of fruit juice.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 20, 2018
    Applicant: National Agriculture and Food Research Organization
    Inventors: Terutaka Yoshioka, Toshio Yoshida, Hirohisa Nesumi, Satoshi Ota, Masayuki Kita, Takeshi Kuniga, Mutsuko Nonomura, Naoko Nakajima, Hiroko Hamada, Keisuke Nonaka, Fumitaka Takishita
  • Publication number: 20180349139
    Abstract: A Load and Store Queue (LDSTQ) stores load store instructions therein with an upper limit being a first number, and sequentially outputs the stored load store instructions to cause a data cache or a main memory to execute processing of data in accordance with the output load store instructions. A decode unit acquires load store instructions, and determines a queued number of load store instructions which have not been output from the LDSTQ among load store instructions output from the decode unit. When the queued number is smaller than a second number which is larger than the first number, the decode unit outputs the acquired load store instructions. An LDSTQ management unit acquires the output load store instructions. When the stored number of load store instructions stored in the LDSTQ is smaller than the first number, the LDSTQ management unit stores the acquired load store instructions in the LDSTQ.
    Type: Application
    Filed: May 10, 2018
    Publication date: December 6, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Sota SAKASHITA, Toshio YOSHIDA
  • Patent number: 10031101
    Abstract: An ion sensor is configured such that part of a P well on which part a sensing section is provided is different, in dopant concentration, from the other part of the P well so that electric charges are injected merely to the sensing section in a state where a voltage is applied to an N-type substrate.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: July 24, 2018
    Assignees: SHARP KABUSHIKI KAISHA, NATIONAL UNIVERSITY CORP TOYOHASHI UNIVERSITY
    Inventors: Satoshi Saitoh, Toshio Yoshida, Tomohiro Konishi, Kazuaki Sawada
  • Publication number: 20170041560
    Abstract: A light detecting device includes: an optical filter (2) that transmits a first wavelength light having a wavelength in a first wavelength range, a second wavelength light having a wavelength in a second wavelength range, . . . , and an n-th wavelength light having a wavelength in an n-th wavelength range (n is an integer); an optical sensor (3) that detects at least one of a first wavelength light intensity of the first wavelength light, a second wavelength light intensity of the second wavelength light, . . . , and an n-th wavelength light intensity of the n-th wavelength light; and an analysis unit (4) that estimates a light intensity of light having a wavelength in a wavelength range other than at least one of the first wavelength range, the second wavelength range, . . . , and the n-th wavelength range based on at least one of the first wavelength light intensity, the second wavelength light intensity, . . . , and the n-th wavelength light intensity.
    Type: Application
    Filed: March 23, 2015
    Publication date: February 9, 2017
    Inventors: Toshihisa GOTOH, Toshio YOSHIDA, Yoshinobu KANAZAWA, Yoshimitsu NAKASHIMA, Kohji KOBAYASHI, Toshio FUKAI, Hitoshi AOKI, Yasushi NAGAMUNE, Takashi TOKIZAKI, Toshitaka OTA
  • Patent number: 9442836
    Abstract: An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation, and a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction relating to the memory allocation area.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: September 13, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Shuji Yamamura, Masaharu Maruyama, Toshio Yoshida, Ryuji Kan, Naohiro Kiyota, Mikio Hondo, Tsuyoshi Motokurumada
  • Publication number: 20160109404
    Abstract: An ion sensor is configured such that part of a P well on which part a sensing section is provided is different, in dopant concentration, from the other part of the P well so that electric charges are injected merely to the sensing section in a state where a voltage is applied to an N-type substrate.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 21, 2016
    Inventors: Satoshi SAITOH, Toshio YOSHIDA, Tomohiro KONISHI, Kazuaki SAWADA
  • Patent number: 9169869
    Abstract: To provide a side seal capable of preventing the entrance of the foreign matter to the inside of the slider and the outflow of the lubricant without damaging or reducing the original function of the lip, and to provide a linear guide apparatus including the above described side seal. A linear guide apparatus (1) includes a side seal (30) attached to an end of the slider (20) in the axial direction and including a lip portion (33) coming into sliding contact with the guide rail (10). The side seal (30) includes a thin film (40) coming into sliding contact with the guide rail (10) and filling a part of a gap (34) of the lip portion (33).
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: October 27, 2015
    Assignee: NSK Ltd.
    Inventor: Toshio Yoshida
  • Patent number: 9163195
    Abstract: A lubricating oil composition comprising a lubricating base oil, and a mixture and/or a reaction product of (A) 0.01-0.5% by mass of at least one compound selected from among acid phosphates represented by formula (1) or formula (2), and (B) 0.01-2% by mass of an alkylamine represented by formula (3), based on the total weight of the composition, wherein the acid value due to component (A) is 0.1-1.0 mgKOH/g. [R1 and R2 represent hydrogen or straight-chain alkyl or straight-chain alkenyl groups, with at least one of R1 and R2 being a C6-12 straight-chain alkyl or straight-chain alkenyl group; R3 and R4 represent hydrogen straight-chain alkyl or straight-chain alkenyl groups, with at least one of R3 and R4 being a C13-18 straight-chain alkyl or straight-chain alkenyl group; and R5 and R6 represent hydrogen or C4-30 branched-chain alkyl groups, with at least one of R5 and R6 being a branched-chain alkyl group.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: October 20, 2015
    Assignee: JX NIPPON OIL & ENERGY CORPORATION
    Inventors: Hajime Nakao, Shozaburo Konishi, Toshio Yoshida
  • Patent number: 9042861
    Abstract: An emergency wireless connection system which operates as a normal information terminal in normal times and operates as a terminal to send and receive emergency information in emergency situation includes a line detection unit which detects an emergency communication network capable of communicating when emergency situation occurs, and a control unit which makes the emergency wireless connection system conform to a procedure of the emergency communication network based on channel information of the emergency communication network detected by the line detection unit.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: May 26, 2015
    Assignee: NEC CORPORATION
    Inventor: Toshio Yoshida
  • Publication number: 20150089180
    Abstract: An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation, and a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction relating to the memory allocation area.
    Type: Application
    Filed: August 21, 2014
    Publication date: March 26, 2015
    Inventors: Shuji Yamamura, Masaharu Maruyama, Toshio Yoshida, RYUJI KAN, NAOHIRO KIYOTA, Mikio Hondo, TSUYOSHI MOTOKURUMADA
  • Publication number: 20140321777
    Abstract: To provide a side seal capable of preventing the entrance of the foreign matter to the inside of the slider and the outflow of the lubricant without damaging or reducing the original function of the lip, and to provide a linear guide apparatus including the above described side seal. A linear guide apparatus (1) includes a side seal (30) attached to an end of the slider (20) in the axial direction and including a lip portion (33) coming into sliding contact with the guide rail (10). The side seal (30) includes a thin film (40) coming into sliding contact with the guide rail (10) and filling a part of a gap (34) of the lip portion (33).
    Type: Application
    Filed: September 19, 2012
    Publication date: October 30, 2014
    Applicant: NSK Ltd.
    Inventor: Toshio Yoshida
  • Publication number: 20140249060
    Abstract: A lubricating oil composition comprising a lubricating base oil, and a mixture and/or a reaction product of (A) 0.01-0.5% by mass of at least one compound selected from among acid phosphates represented by formula (1) or formula (2), and (B) 0.01-2% by mass of an alkylamine represented by formula (3), based on the total weight of the composition, wherein the acid value due to component (A) is 0.1-1.0 mgKOH/g. [R1 and R2 represent hydrogen or straight-chain alkyl or straight-chain alkenyl groups, with at least one of R1 and R2 being a C6-12 straight-chain alkyl or straight-chain alkenyl group; R3 and R4 represent hydrogen straight-chain alkyl or straight-chain alkenyl groups, with at least one of R3 and R4 being a C13-18 straight-chain alkyl or straight-chain alkenyl group; and R5 and R6 represent hydrogen or C4-30 branched-chain alkyl groups, with at least one of R5 and R6 being a branched-chain alkyl group.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 4, 2014
    Applicant: JX NIPPON OIL & ENERGY CORPORATION
    Inventors: Hajime NAKAO, Shozaburo KONISHI, Toshio YOSHIDA
  • Publication number: 20140068299
    Abstract: When a result of detection by a current sensor 22 represents the occurrence of an overcurrent, comparators 23 of PSUs 2 transmit a present report indicating that fact to an SP 1. Receiving the present report, an FPGA 12 of the SP 1 turns on a forcible low-power signal. A forcible power saving control circuit 32 of a CPU 3 directly inputs a forcible-low-power-mode signal, turns on the signal, and controls an instruction issuance control unit that is configured to issue an instruction in the CPU 3, so as to immediately decrease the frequency at which the instruction issuance control unit issues instructions. This control is cancelled after the DVFS control circuit 35 has reduced the voltage of power output from a DDC 4 and a clock frequency output from a PLL circuit.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 6, 2014
    Applicant: FUJITSU LIMITED
    Inventors: HIDEYUKI KOINUMA, HIROMI FUKUMURA, MICHIHARU HARA, HIRONOBU KAGEYAMA, TOSHIO YOSHIDA
  • Patent number: PP31146
    Abstract: A new and distinct variety of Citrus L. plant named ‘ASUKI’, characterized by being late-maturing, having high brix and excellent taste, being easy to eat because of its soft segment membrane, having no occurrence of fruit rind puffing, and having less dripping of fruit juice.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 3, 2019
    Assignee: National Agriculture and Food Research Organization
    Inventors: Terutaka Yoshioka, Toshio Yoshida, Hirohisa Nesumi, Satoshi Ota, Masayuki Kita, Takeshi Kuniga, Mutsuko Nonomura, Naoko Nakajima, Hiroko Hamada, Keisuke Nonaka, Fumitaka Takishita