Abstract: The present invention relates to a multithread processor, and this multithread processor comprises a plurality of register windows each provided for each of threads and capable of storing data to be used for instruction processing in an arithmetic unit, a work register capable of mutually transferring data with respect to the plurality of register windows and the arithmetic unit and a multithread control unit for controlling data transfer among the plurality of register windows, the work register and the arithmetic unit on the basis of an execution thread identifier for identifying the thread to be executed in the arithmetic unit. This enables conducting the multithread processing at a high speed.

Abstract: The present invention relates to a multithread processor, and this multithread processor comprises a plurality of register windows each provided for each of threads and capable of storing data to be used for instruction processing in an arithmetic unit, a work register capable of mutually transferring data with respect to the plurality of register windows and the arithmetic unit and a multithread control unit for controlling data transfer among the plurality of register windows, the work register and the arithmetic unit on the basis of an execution thread identifier for identifying the thread to be executed in the arithmetic unit. This enables conducting the multithread processing at a high speed.

Abstract: A fiber switching mechanism of a lighting system for passing a light through one of n optical fibers corresponding to n channels sequentially is provided midway in n optical fibers of the lighting system corresponding to n channels such that lights from n optical fibers of a receiving system can be commonly received by a single spectroscope. With the fiber switching mechanism of the lighting system, it is possible to obtain measuring data of reflection spectrum of n optical thin film sensor portions by the single spectroscope.

Abstract: The present invention includes a decode section for simultaneously holding a plurality of instructions in one thread at a time and for decoding the held instructions; an execution pipeline capable of simultaneously executing each processing represented by the respective instructions belonging to different threads and decoded by the decode section; a reservation station for receiving the instructions decoded by the decode section and holding the instructions, if the decoded instructions are of sync attribute, until executable conditions are ready and thereafter dispatching the decoded instructions to the execution pipeline; a pre-decode section for confirming by a simple decoding, prior to decoding by the decode section, whether or not the instructions are of sync attribute; and an instruction buffer for suspending issuance to the decode section and holding the instructions subsequent to an instruction of sync attribute.

Abstract: In a CPU having a SMT function of executing plural threads composed of a series of instructions representing processing, there are provided a decode section for decoding processing represented by instructions of plural threads, an instruction buffer for obtaining instructions from a thread and holding the instructions, and inputting the held instructions to the decode section in order in the thread, and an execution pipeline for executing processing of instructions decoded by the decode section. The decode section checks whether or not an executable condition is ready for an instruction when the instruction is decoded and requests that the instructions held in the instruction buffer and an instruction subsequent to an instruction that is not ready with an executable condition are inputted again to the decode section.

Abstract: An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.

Abstract: An instruction processing apparatus includes a thread execution processing section executing threads each including plural instructions, a register file including a register window having plural registers, a current window pointer indicating a position of the register where the register window is possible to be inputted and outputted, a current register reading data held by the register window designated by the current window pointer to hold the data and a replacement buffer holding data transferred from the register file to the current register, a first transfer path transferring data in a register file to one of the replacement buffer, a second data transfer transferring data in a replacement buffer to one of the current registers, a calculation section executing a switching instruction of the register window, and a control section controlling, if the calculation section executes the switching instruction, the first data transfer path and the second data transfer path.

Abstract: An information processing apparatus and a method of controlling the same that employs a register window system and a Simultaneous Multithreading method for reducing circuit areas by sharing a data transfer bus between threads, said bus connecting a master register and a work register provided for each thread and for avoiding interference in instruction execution with other threads caused by a conflict between accesses to a register between threads. An information processing apparatus and a method of controlling the information processing apparatus employing a register window system for register reading, in which a master register and a work register are held for each thread and a bus for transferring data from the master to the work register is shared by threads in order to realize Simultaneous Multithreading.

Abstract: The present invention provides a refrigerating machine oil, a compressor oil composition, a hydraulic oil composition, a metalworking oil composition, a heat treating oil composition, a lubricating oil composition for machine tools and a lubricating oil composition which comprise a lubricating oil base oil having % CA of not more than 2, % CP/% CN of not less than 6 and an iodine value of not more than 2.5.

Abstract: An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. And the instruction execution control device has a thread selection circuit (30) which detects a state where an instruction has not been completed for a predetermined period during simultaneous multi-thread operation, and controls such that all the reservation stations (5, 6 and 7) can execute only a predetermined thread. Therefore if an entry that cannot be executed from the reservation stations (5, 6 and 7) exists, execution of an entry in the thread that cannot be executed can be enabled by stopping the execution of the thread which has been executed continuously.

Abstract: The information processing device in the simultaneous multi-threading system is operated in an inter-thread performance load arbitration control method, and includes: an instruction input control unit for sharing among threads control of inputting an instruction in an arithmetic unit for acquiring the instruction from memory and performing an operation on the basis of the instruction; a commit stack entry provided for each thread for holding information obtained by decoding the instruction; an instruction completion order control unit for updating the memory and a general purpose register depending on an arithmetic result obtained by the arithmetic unit in an order of the instructions input from the instruction input control unit; and a performance load balance analysis unit for detecting the information registered in the commit stack entry and controlling the instruction input control unit.

Abstract: An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device 100 includes: an instruction execution circuit 101 capable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuit 102 instructing the instruction execution circuit 101 to switch a thread mode.

Abstract: A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register.

Abstract: There is provided a portable electronic device capable of being immediately operated without the use of a battery even when the battery reaches exhaustion. An electricity generating unit 131 is embedded in the portable electronic device. The electricity generating unit 131 has a mechanism to pull out a pull line 113 wound around a pulley 135 to wind up a spiral spring 133 and a mechanism to transfer torque occurring when the spiral spring 133 is released and to rotate the motor at high speed. An output voltage from the motor 142 is adjusted and smoothed by a constant voltage circuit and is directly supplied as power to power consuming components. The portable electronic device connecting two flips can wind up the spiral spring 133 by opening and closing the two flips.

Abstract: A detection of an anomaly of geomagnetism and a collection of data are performed by using portable telephones. Direction variations measured by geomagnetic sensors mounted to the portable telephones are collected via data transmission lines for portable telephones, and the variations are observed for each area. Earthquake occurrence warning information is transmitted to a portable terminal of a collaborator for geomagnetism information provision in an area in which a number of occurrences of the variations is significantly large.

Abstract: A canister includes a canister case having an adsorbent chamber, an adsorbent housed in the adsorbent chamber of the canister case, a filter disposed between the adsorbent chamber and a port mounted on an end wall of the adsorbent chamber, and a tentative filter engaging projection provided in the adsorbent chamber. The filter is loosely fitted within the adsorbent chamber and then welded on the end wall of the adsorbent chamber. The tentative filter engaging projection tentatively holds the filter loosely fitted within the adsorbent chamber in a welding step of the filter.

Abstract: A slider has a slider main body which has a circulation sleeve whose inner portion forms a rolling element passage by being inserted into a hole penetrating in an axial direction, an end cap which has an outer peripheral track face of a direction changing passage in a curved shape for communicating a load track between two rolling element rolling grooves and the rolling element passage, and is fixed to an axial end portion of the slider main body, and an inner peripheral track member which has an inner peripheral track face of the direction changing passage, and is fitted to the end cap. An end portion of the circulation sleeve is provided with a plurality of positioning projected portions, and the end cap and the inner peripheral track member are provided with recess portions fitted with the positioning projected portions.

Abstract: A processor capable of executing conditional store instructions without being limited by the number of condition codes is provided. Condition data is stored in floating-point registers, and an operation unit executes a conditional floating-point store instruction of determining whether to store, in cache, store data.

Abstract: A single-precision floating-point data storing method for use in a processor including a register, which has a size that can store double-precision floating-point data, for storing double-precision floating-point data and single-precision floating-point data comprises writing input single-precision floating-point data to the high-order half of the register, and writing all zeros to the low-order half of the register if a single-precision floating-point data process is specified.

Abstract: A latest register update buffer which stores latest register update data is allocated and prepared every general register for storing source data. A latest register update processing unit stores a value in the general register as latest register update data into the latest register update buffer when a register update instruction is not speculatively executed, and overwrites a result of the speculative execution when the instruction is speculatively executed. Upon instruction decoding, a matching processing unit reads out the latest register update data from the latest register update allocation buffer and stores it into a data area in a reservation station.