Patents by Inventor Toshiro Futatsugi

Toshiro Futatsugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190103502
    Abstract: Provided is a semiconductor light detection device having a relatively high detection sensitivity to a light component of a specific wavelength. The semiconductor light detection device includes: a semiconductor light receiving element, in which a first conductive layer is formed on a surface of a semiconductor substrate, a second conductive layer is formed below the first conductive layer, a third conductive layer is formed below the second conductive layer, and a photocurrent based on the intensity of incident light is output from the third conductive layer while an input voltage is applied to the first conductive layer; and a semiconductor detection circuit configured to output an output voltage based on a current difference between a first photocurrent and a second photocurrent being output in response to the application of the first input voltage and the second input voltage, respectively.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 4, 2019
    Inventor: Toshiro FUTATSUGI
  • Publication number: 20190096928
    Abstract: Provided is an ultraviolet light receiving element capable of reducing visible light sensitivity. The ultraviolet light receiving element includes: a first photodiode sensitive to an ultraviolet light provided in a first region of a semiconductor substrate; and a second photodiode insensitive to the ultraviolet light provided in a second region of the semiconductor substrate. A second well implantation layer in the second photodiode has a peak concentration position deeper than a peak concentration position of a well implantation layer in the first photodiode by a depth equal to a depth from a surface of the semiconductor substrate to a peak concentration position of a surface implantation layer in the second photodiode.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 28, 2019
    Inventors: Kazusa OKUDA, Toshiro FUTATSUGI
  • Patent number: 10191006
    Abstract: A humidity sensor includes an insulating film formed on a semiconductor substrate, and a plurality of first electrodes and a plurality of second electrodes arranged on the insulating film so that each first electrode is adjacent to four of the second electrodes in four directions of up, down, right, and left when viewed in plan view, while each second electrode is adjacent to four of the first electrodes in four directions of up, down, right, and left when viewed in plan view. Metal wiring embedded in the insulating film electrically connects one of the first electrodes to another of the first electrodes, and electrically connects one of the second electrodes to another of the second electrodes. The humidity sensor has increased capacitance per unit area and improved adhesiveness and can be made using normal semiconductor manufacturing processes.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: January 29, 2019
    Assignee: ABLIC INC.
    Inventor: Toshiro Futatsugi
  • Publication number: 20180323233
    Abstract: In order to form a light receiving element having high reliability and a MOS transistor together on the same silicon substrate, after forming a gate electrode of the MOS transistor, a gate oxide film in a light receiving element forming region is removed. Then, a thermal oxide film is newly formed in the light receiving element forming region, and ion implantation is performed in the light receiving element forming region through the thermal oxide film such that a shallow pn junction is formed.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventor: Toshiro FUTATSUGI
  • Patent number: 10043848
    Abstract: In order to form a light receiving element having high reliability and a MOS transistor together on the same silicon substrate, after forming a gate electrode of the MOS transistor, a gate oxide film in a light receiving element forming region is removed. Then, a thermal oxide film is newly formed in the light receiving element forming region, and ion implantation is performed in the light receiving element forming region through the thermal oxide film such that a shallow pn junction is formed.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 7, 2018
    Assignee: SII Semiconductor Corporation
    Inventor: Toshiro Futatsugi
  • Publication number: 20170256582
    Abstract: In order to form a light receiving element having high reliability and a MOS transistor together on the same silicon substrate, after forming a gate electrode of the MOS transistor, a gate oxide film in a light receiving element forming region is removed. Then, a thermal oxide film is newly formed in the light receiving element forming region, and ion implantation is performed in the light receiving element forming region through the thermal oxide film such that a shallow pn junction is formed.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 7, 2017
    Inventor: Toshiro FUTATSUGI
  • Publication number: 20160258894
    Abstract: Provided is a humidity sensor that is increased in capacitance per unit area and is improved in the close adhesiveness and ease of embedding of a humidity sensitive film, while being capable of fitting into normal semiconductor manufacturing processes. A plurality of first electrodes and a plurality of second electrodes are arranged so that each first electrode is adjacent to four of the second electrodes in four directions of up, down, right, and left when viewed in plan view, while each second electrode is adjacent to four of the first electrodes in four directions of up, down, right, and left when viewed in plan view. Metal wiring electrically connects one of the first electrodes to another of the first electrodes, and electrically connects one of the second electrodes to another of the second electrodes.
    Type: Application
    Filed: February 23, 2016
    Publication date: September 8, 2016
    Inventor: Toshiro FUTATSUGI
  • Patent number: 8013379
    Abstract: The semiconductor variable capacitor includes a capacitor including an n-well 16 formed in a first region of a semiconductor substrate 10, an insulating film 18 formed over the semiconductor substrate 10 and a gate electrode 20n formed above the n-well 16 with the insulating film 18 interposed therebetween; and a p-well 14 of a second conduction type formed in a second region adjacent to the first region of the semiconductor substrate 10. The gate electrode 20n has an end which is extended to the second region and formed above the p-well 14 with the insulating film 18 interposed therebetween.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: September 6, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Toshiro Futatsugi
  • Patent number: 7468297
    Abstract: A method of manufacturing semiconductor device comprising forms a first impurity diffusion region as a lower electrode of a capacitor in a first area of a semiconductor substrate by implanting impurities at a first dose; forms a second impurity diffusion region in a second area, at the end part of the semiconductor substrate, by implanting impurities at a second dose; and forms, by a thermal oxidation method, a capacitor insulation film having a first thickness on the first impurity diffusion region and forms an oxide film having a second thickness which is thicker than the first thickness on the second area.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: December 23, 2008
    Assignee: Fujitsu Limited
    Inventors: Toshiro Futatsugi, Naoto Horiguchi, Ken-ichi Okabe, Kenichi Hikazutani
  • Publication number: 20080237677
    Abstract: The semiconductor variable capacitor includes a capacitor including an n-well 16 formed in a first region of a semiconductor substrate 10, an insulating film 18 formed over the semiconductor substrate 10 and a gate electrode 20n formed above the n-well 16 with the insulating film 18 interposed therebetween; and a p-well 14 of a second conduction type formed in a second region adjacent to the first region of the semiconductor substrate 10. The gate electrode 20n has an end which is extended to the second region and formed above the p-well 14 with the insulating film 18 interposed therebetween.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Toshiro FUTATSUGI
  • Publication number: 20050221556
    Abstract: A method of manufacturing semiconductor device comprising forms a first impurity diffusion region as a lower electrode of a capacitor in a first area of a semiconductor substrate by implanting impurities at a first dose; forms a second impurity diffusion region in a second area, at the end part of the semiconductor substrate, by implanting impurities at a second dose; and forms, by a thermal oxidation method, a capacitor insulation film having a first thickness on the first impurity diffusion region and forms an oxide film having a second thickness which is thicker than the first thickness on the second area.
    Type: Application
    Filed: April 6, 2005
    Publication date: October 6, 2005
    Inventors: Toshiro Futatsugi, Naoto Horiguchi, Ken-ichi Okabe, Kenichi Hikazutani
  • Patent number: 6774430
    Abstract: A non-volatile semiconductor memory comprising a semiconductor substrate, a gate insulating film formed on the substrate, and having a thin central section and thick end sections, a floating gate formed on the rate insulating film, an inter-electrode insulating film formed on the floating gate, a control gate formed on the inter-electrode insulating film, and source/drain regions formed in the substrate on both sides of the floating sate and having extensions extending under the thick end sections of the floating gate, and separated from the thin central section of the gate insulating film, wherein the thin central section enables tunneling of carriers at a low applied voltage, and thick end sections prevent tunneling of stored charges to the extensions and enhance retention of the stored charges.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: August 10, 2004
    Assignee: Fujitsu Limited
    Inventors: Naoto Horiguchi, Toshiro Futatsugi
  • Patent number: 6480420
    Abstract: A semiconductor memory device having a plurality of memory cells, word lines and bit lines formed on a semiconductor substrate, where each of the memory cells includes a source area formed adjacent to a channel area in the semiconductor substrate; a drain area formed opposite the source area with the channel area therebetween in the semiconductor substrate, the drain area being connected to one of the bit lines; a tunnel insulating film formed on the channel area, the tunnel insulating film having a proper thickness for a carrier to pass through by a tunnel phenomenon; a floating gate formed on the tunnel insulating film so as to overlap neither the source area nor the drain area; a gate insulating film formed on the floating gate so as to cover the floating gate; and a control gate formed on the gate insulating film so as to partially overlap both of the source area and the drain area, the control gate being connected to one of the word lines.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: November 12, 2002
    Assignee: Fujitsu Limited
    Inventor: Toshiro Futatsugi
  • Publication number: 20020079533
    Abstract: A semiconductor memory device manufacturing method includes the steps of (a) forming a stack of a first gate insulating layer, a floating gate electrode layer, an inter-electrode insulating layer, and a control electrode layer on a semiconductor substrate; (b) patterning the stack using a mask and thereby creating a gate electrode pattern; (c) causing a chemical reaction for the gate electrode pattern from both sides thereof and increasing thereby the thickness of the gate insulating layer at the end sections; and (d) implanting ions of impurity in the active regions on both sides of the gate electrode pattern and forming thereby first source/drain regions respectively extending into regions respectively below the end sections of the gate insulating layer. In the semiconductor memory device, a tunnel oxide film can be thinned and reduction in retention time of memory information can be prevented.
    Type: Application
    Filed: October 29, 2001
    Publication date: June 27, 2002
    Applicant: Fujitsu Limited
    Inventors: Naoto Horiguchi, Toshiro Futatsugi
  • Publication number: 20020031009
    Abstract: A semiconductor memory device has a plurality of memory cells, word lines and bit lines formed on a semiconductor substrate. Each of the memory cells comprising a source area formed adjacent to a channel area in the semiconductor substrate; a drain area formed opposite the source area with the channel area therebetween in the semiconductor substrate, the drain area being connected to one of the bit lines; a tunnel insulating film formed on the channel area, the tunnel insulating film having a proper thickness for a carrier to pass through by a tunnel phenomenon; a floating gate formed on the tunnel insulating film so as to overlap neither the source area nor the drain area; a gate insulating film formed on the floating gate so as to cover the floating gate; and a control gate formed on the gate insulating film so as to partially overlap both of the source area and the drain area, the control gate being connected to one of the word lines.
    Type: Application
    Filed: March 28, 2001
    Publication date: March 14, 2002
    Applicant: Fujitsu Limited
    Inventor: Toshiro Futatsugi
  • Patent number: 6294794
    Abstract: A non-linear optical device includes a plurality of quantum dots in an active layer such that the quantum dots have a composition or doping modified asymmetric in a direction perpendicular to the active layer.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: September 25, 2001
    Assignee: Fujitsu Limited
    Inventors: Tetsuzo Yoshimura, Toshiro Futatsugi
  • Patent number: 6195292
    Abstract: A source region and a drain region are formed in a surface layer of a semiconductor substrate on both sides of a channel region defined in the surface layer. A tunneling insulating film is formed on the channel region, the tunneling insulating film having a thickness which allows carriers to tunnel therethrough. A floating gate electrode is formed on the tunneling insulating film, the floating gate electrode being disposed so as to overlap neither the source region nor the drain region as viewed along a substrate normal direction. A gate insulating film is formed over the channel region, covering the floating gate electrode. A control gate electrode is formed on the gate insulating film, the control gate electrode being disposed so as to become in contact with, or partially overlap, the source and drain regions as viewed along the substrate normal direction.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: February 27, 2001
    Assignee: Fujitsu Limited
    Inventors: Tatsuya Usuki, Toshiro Futatsugi
  • Patent number: 5889288
    Abstract: A semiconductor quantum dot device using a semiconductor quantum dot comprises a semiconductor quantum dot formed on a semiconductor wafer, a field effect transistor formed on said semiconductor wafer and comprising a gate electrode formed in a vicinity of said semiconductor quantum dot, and a coupling means to couple said gate electrode and said semiconductor quantum dot capacitively.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventor: Toshiro Futatsugi
  • Patent number: 5031005
    Abstract: A semiconductor device comprises stacked first through fifth semiconductor layers. The semiconductor device has an energy level condition of .vertline.Ec.sub.3 -Ec.sub.1 .vertline..apprxeq..vertline.Ev.sub.3 -Ev.sub.5 .vertline., where Ec.sub.3 is a resonant energy level of electrons in a conduction band of the third layer and Ev.sub.3 is a resonant energy level of holes in a valence band thereof, and Ec.sub.1 is an energy level of a conduction band of the first layer and Ev.sub.5 is an energy level of a valence band of the fifth layer.
    Type: Grant
    Filed: October 21, 1987
    Date of Patent: July 9, 1991
    Assignee: Fujitsu Limited
    Inventors: Toshiro Futatsugi, Naoki Yokoyama, Kenichi Imamura
  • Patent number: 4907196
    Abstract: A semiconductor memory device comprises a transistor having such a current characteristic that a base current has a differential negative resistance characteristic and a collector current greatly flows after the differential negative resistance characteristic occurs in the base current when a base-emitter voltage is increased, a load coupled in series between a collector and a base of the transistor, first and second input terminals coupled to the base of the transistor through a base resistance of the transistor, and an ouptut terminal coupled to the collector of the transistor.
    Type: Grant
    Filed: April 21, 1988
    Date of Patent: March 6, 1990
    Assignee: Fujitsu Limited
    Inventors: Toshihiko Mori, Toshiro Futatsugi