Abstract: A semiconductor quantum dot device using a semiconductor quantum dot comprises a semiconductor quantum dot formed on a semiconductor wafer, a field effect transistor formed on said semiconductor wafer and comprising a gate electrode formed in a vicinity of said semiconductor quantum dot, and a coupling means to couple said gate electrode and said semiconductor quantum dot capacitively.

Abstract: A semiconductor device comprises stacked first through fifth semiconductor layers. The semiconductor device has an energy level condition of .vertline.Ec.sub.3 -Ec.sub.1 .vertline..apprxeq..vertline.Ev.sub.3 -Ev.sub.5 .vertline., where Ec.sub.3 is a resonant energy level of electrons in a conduction band of the third layer and Ev.sub.3 is a resonant energy level of holes in a valence band thereof, and Ec.sub.1 is an energy level of a conduction band of the first layer and Ev.sub.5 is an energy level of a valence band of the fifth layer.

Abstract: A semiconductor memory device comprises a transistor having such a current characteristic that a base current has a differential negative resistance characteristic and a collector current greatly flows after the differential negative resistance characteristic occurs in the base current when a base-emitter voltage is increased, a load coupled in series between a collector and a base of the transistor, first and second input terminals coupled to the base of the transistor through a base resistance of the transistor, and an ouptut terminal coupled to the collector of the transistor.

Abstract: An electrode structure of an electrode of a refractory metal or a silicide thereof on a layer of In.sub.x Ga.sub.1-x As (0<x<1) on a substrate of a III-V compound semiconductor is ohmic and is stable even at a high temperature, for example, 900.degree. C. This high temperature stable ohmic electrode structure allows ion implantation into the substrate with the electrode as a mask followed by annealing to form a doped region in alignment with the edge of the electrode.

Abstract: A semiconductor device comprises a first barrier layer, a quantum well layer formed on the first barrier layer and having a bottom of conduction band with an energy which varies with a curve of second order, a second barrier layer formed on said quantum well layer, and first and second contact layers. The first barrier layer, the quantum well layer and the second barrier layer make up a layer sequence which is repeated a predetermined number of times, and the first contact layer connects to the first barrier layer in a first of the predetermined number of layer sequences, while the second contact layer connects to the second barrier layer in a last of the predetermined number of layer sequences.

Abstract: In a semiconductor integrated circuit device, a plurality of a field effect transistors are formed on a (110) crystal surface of a group III-V compound semiconductor substrate having a zinc blend type crystal structure.

Abstract: An IC device comprising a plurality of FET's using a compound semiconductor, more specifically, a zincblende type semiconductor substrate, having a surface of a (111) plane. By use of this plane, differences of characteristics of the FET's depending on directions along which gates of the FET's are arranged when the gate length is made shorter are prevented, allowing arrangement of gates of the FET's in different directions, particularly perpendicular to each other, with making the gate length shorter to miniaturize and densify the device.