Patents by Inventor Toshishige Shimamura

Toshishige Shimamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7480785
    Abstract: A row decoding circuit (171) outputs a select signal to a row set in a row range setting unit (172) to select a select signal line (103), processing results from processing circuits (102) on this row are output to a data output line (104), and a row adder (106) adds processing results output to a data output line (104) of a column set in a column range selector (105).
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: January 20, 2009
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Toshishige Shimamura, Hiroki Morimura, Koji Fujii, Satoshi Shigematsu, Katsuyuki Machida
  • Publication number: 20080187192
    Abstract: A detection element (1A) having a detection electrode (11A) connected to a surface shape detection unit (2) and a detection electrode (12A) connected to a common potential, and a detection element (1B) having a detection electrode (11B) connected to the surface shape detection unit (2) and a detection electrode (12B) connected to a biometric recognition unit (3) are arranged. The surface shape detection unit (2) outputs a signal representing the three-dimensional pattern of the surface shape corresponding to the contact portion to each detection element on the basis of individual capacitances obtained from the detection elements (1A, 1B). The biometric recognition unit (3) determines whether an object (9) is a living body, on the basis of a signal corresponding to the impedance of the object (9) connected between the detection electrode (12B) of the detection element (1B) and the detection electrode (12A) of the detection element (1A).
    Type: Application
    Filed: March 28, 2008
    Publication date: August 7, 2008
    Inventors: Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Norio Sato, Masami Urano, Katsuyuki Machida
  • Patent number: 7366332
    Abstract: A detection element (1A) having a detection electrode (11A) connected to a surface shape detection unit (2) and a detection electrode (12A) connected to a common potential, and a detection element (1B) having a detection electrode (11B) connected to the surface shape detection unit (2) and a detection electrode (12B) connected to a biometric recognition unit (3) are arranged. The surface shape detection unit (2) outputs a signal representing the three-dimensional pattern of the surface shape corresponding to the contact portion to each detection element on the basis of individual capacitances obtained from the detection elements (1A, 1B). The biometric recognition unit (3) determines whether an object (9) is a living body, on the basis of a signal corresponding to the impedance of the object (9) connected between the detection electrode (12B) of the detection element (1B) and the detection electrode (12A) of the detection element (1A).
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: April 29, 2008
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Norio Sato, Masami Urano, Katsuyuki Machida
  • Patent number: 7360293
    Abstract: A method of manufacturing a surface shape recognition sensor. A sacrificial film is formed on an interlevel dielectric to cover a lower electrode while keeping an upper portion of a support electrode exposed. An upper electrode is formed on the sacrificial film and support electrode. The sacrificial film is selectively removed and a protective film is formed on the upper electrode. A photosensitive resin film having photosensitivity is formed on the protective film. A plurality of projections are formed in a region of the protective film above a capacitive detection element. In this manner a plurality of capacitive detection elements each having the lower electrode and upper electrode are formed.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: April 22, 2008
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Norio Sato, Katsuyuki Machida, Hakaru Kyuragi, Satoshi Shigematsu, Hiroki Morimura, Hiromu Ishii, Toshishige Shimamura
  • Patent number: 7208809
    Abstract: In a semiconductor device having a MEMS according to this invention, a plurality of units having movable portions for constituting a MEMS are monolithically mounted on a semiconductor substrate on which an integrated circuit including a driving circuit, sensor circuit, memory, and processor is formed. Each unit has a processor, memory, driving circuit, and sensor circuit.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: April 24, 2007
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Masami Urano, Hiromu Ishii, Toshishige Shimamura, Yasuyuki Tanabe, Katsuyuki Machida, Tomomi Sakata
  • Patent number: 7123026
    Abstract: A surface shape recognition sensor includes capacitive detection elements, support electrode, protective film, and projections. The detection elements are formed from lower electrodes and a deformable plate-like upper electrode made of a metal. The lower electrodes are insulated and isolated from each other and stationarily laid out on a single plane of an interlevel dielectric formed on a semiconductor substrate. The upper electrode is laid out above the lower electrodes at a predetermined interval and has opening portions. The support electrode is laid out around the lower electrodes while being insulated and isolated from the lower electrodes, and formed to be higher than the lower electrodes to support the upper electrode. The protective film is formed on the upper electrode to close the opening portions. The projections per one pixel are laid out in a region of the protective film above the capacitive detection element.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: October 17, 2006
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Norio Sato, Katsuyuki Machida, Hakaru Kyuragi, Satoshi Shigematsu, Hiroki Morimura, Hiromu Ishii, Toshishige Shimamura
  • Patent number: 7062075
    Abstract: A calibration mode signal line to which sensor cells are commonly connected is arranged. In a calibration mode, a calibration mode signal is supplied to the sensor cells through the calibration mode signal line to designate calibration. In each sensor cell, when the calibration mode signal is being supplied from the calibration mode signal line, and the sensor cell is selected by the decoder, calibration operation of adjusting the detection sensitivity of a sensor circuit is executed using a calibration circuit.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: June 13, 2006
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroki Morimura, Toshishige Shimamura, Satoshi Shigematsu, Katsuyuki Machida, Hakaru Kyuragi
  • Publication number: 20060115920
    Abstract: In a semiconductor device having a MEMS according to this invention, a plurality of units having movable portions for constituting a MEMS are monolithically mounted on a semiconductor substrate on which an integrated circuit including a driving circuit, sensor circuit, memory, and processor is formed. Each unit has a processor, memory, driving circuit, and sensor circuit.
    Type: Application
    Filed: January 11, 2006
    Publication date: June 1, 2006
    Inventors: Masami Urano, Hiromu Ishii, Toshishige Shimamura, Yasuyuki Tanabe, Katsuyuki Machida, Tomomi Sakata
  • Patent number: 7019563
    Abstract: A first control potential setting means (1) generates a first control potential (N2) which reverses the magnitude relationship with a second control potential (N3) when an input signal (IN) reaches the vicinity of a logical threshold value. A second control potential setting means (2) generates the second control potential (N3) which changes in the same direction as the input signal (IN), in accordance with a change in input signal (IN). An output means (3) includes transistors (Q5, Q6), and generates an output signal (OUT) having a predetermined potential on the basis of the first control potential (N2), the second control potential (N3), and a reset signal (RSET). A reset means (4) turns off the transistor (Q6) while a waveform shaping circuit is in operation.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: March 28, 2006
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroki Morimura, Toshishige Shimamura, Koji Fujii, Satoshi Shigematsu, Yukio Okazaki, Katsuyuki Machida
  • Publication number: 20060034493
    Abstract: A response signal generating unit (3) applies a predetermined supply signal (2S) to a detection element (1) and outputs, as a response signal (3S), a signal which has changed in accordance with the impedance of an object (10) with which the unit is in contact through the detection element (1). A waveform information detection unit (4) detects waveform information corresponding to the impedance of the object (10) on the basis of the response signal (3S) from the response signal generating unit (3), and outputs a detection signal (4S) representing the waveform information. A biometric recognition unit (5) determines on the basis of the detection signal (4S) from the waveform information detection unit (4) whether or not the object (10) is a living body.
    Type: Application
    Filed: August 12, 2004
    Publication date: February 16, 2006
    Inventors: Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Norio Sato, Masami Urano, Katsuyuki Machida
  • Patent number: 6990219
    Abstract: An image capturing apparatus includes an image capturing section and capture control section. The image capturing section converts the shape of an object into an electrical quantity in accordance with the parameter value set in a parameter setting section, and outputs image data representing an image corresponding to the shape of the object. The capture control section receives the image data output from the image capturing section, calculates an evaluation index for evaluating the image quality of the image from the image data. If the evaluation index falls outside the range of a preset reference value, the capture control section changes the parameter value set in the parameter setting section so as to make the evaluation index fall within the range of the reference value to output the image data which is received from the image capturing section and the evaluation index of which falls within the range of the reference value.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: January 24, 2006
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroki Morimura, Toshishige Shimamura, Kenichi Saito, Yukio Okazaki, Hakaru Kyuragi, Chikara Yamaguchi, Hiroki Suto, Satoshi Shigematsu
  • Publication number: 20050259502
    Abstract: A row decoding circuit (171) outputs a select signal to a row set in a row range setting unit (172) to select a select signal line (103), processing results from processing circuits (102) on this row are output to a data output line (104), and a row adder (106) adds processing results output to a data output line (104) of a column set in a column range selector (105).
    Type: Application
    Filed: February 13, 2004
    Publication date: November 24, 2005
    Inventors: Toshishige Shimamura, Hiroki Morimura, Koji Fujii, Satoshi Shigematsu, Katsuyuki Machida
  • Publication number: 20050258877
    Abstract: A first control potential setting means (1) generates a first control potential (N2) which reverses the magnitude relationship with a second control potential (N3) when an input signal (IN) reaches the vicinity of a logical threshold value. A second control potential setting means (2) generates the second control potential (N3) which changes in the same direction as the input signal (IN), in accordance with a change in input signal (IN). An output means (3) includes transistors (Q5, Q6), and generates an output signal (OUT) having a predetermined potential on the basis of the first control potential (N2), the second control potential (N3), and a reset signal (RSET). A reset means (4) turns off the transistor (Q6) while a waveform shaping circuit is in operation.
    Type: Application
    Filed: January 21, 2004
    Publication date: November 24, 2005
    Applicant: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroki Morimura, Toshishige Shimamura, Koji Fujii, Satoshi Shigematsu, Yukio Okazaki, Katsuyuki Machida
  • Publication number: 20050259850
    Abstract: A detection element (1A) having a detection electrode (11A) connected to a surface shape detection unit (2) and a detection electrode (12A) connected to a common potential, and a detection element (1B) having a detection electrode (11B) connected to the surface shape detection unit (2) and a detection electrode (12B) connected to a biometric recognition unit (3) are arranged. The surface shape detection unit (2) outputs a signal representing the three-dimensional pattern of the surface shape corresponding to the contact portion to each detection element on the basis of individual capacitances obtained from the detection elements (1A, 1B). The biometric recognition unit (3) determines whether an object (9) is a living body, on the basis of a signal corresponding to the impedance of the object (9) connected between the detection electrode (12B) of the detection element (1B) and the detection electrode (12A) of the detection element (1A).
    Type: Application
    Filed: August 12, 2004
    Publication date: November 24, 2005
    Inventors: Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Norio Sato, Masami Urano, Katsuyuki Machida
  • Publication number: 20050214960
    Abstract: A method of manufacturing a surface shape recognition sensor. A sacrificial film is formed on an interlevel dielectric to cover a lower electrode while keeping an upper portion of a support electrode exposed. An upper electrode is formed on the sacrificial film and support electrode. The sacrificial film is selectively removed and a protective film is formed on the upper electrode. A photosensitive resin film having photosensitivity is formed on the protective film. A plurality of projections are formed in a region of the protective film above a capacitive detection element. In this manner a plurality of capacitive detection elements each having the lower electrode and upper electrode are formed.
    Type: Application
    Filed: April 7, 2005
    Publication date: September 29, 2005
    Inventors: Norio Sato, Katsuyuki Machida, Hakaru Kyuragi, Satoshi Shigematsu, Hiroki Morimura, Hiromu Ishii, Toshishige Shimamura
  • Patent number: 6912336
    Abstract: An optical switch device includes at least an optical switch element and driving control circuit. In the optical switch element, a fixed electrode portion is arranged, via a dielectric layer, on a semiconductor substrate on which an integrated circuit is formed. A mirror structure has a plate-shaped movable portion arranged above the fixed electrode portion while opposing the fixed electrode portion. A reflecting portion is formed at least at part of the movable portion to reflect light. A support member is fixed around the fixed electrode portion on the semiconductor substrate via a dielectric layer and supports the mirror structure. The driving control circuit is incorporated in the integrated circuit to drive the optical switch element by applying a predetermined potential to the movable portion and fixed electrode portion.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: June 28, 2005
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiromu Ishii, Yasuyuki Tanabe, Katsuyuki Machida, Masami Urano, Toshishige Shimamura, Yuji Uenishi, Takanori Kiyokura
  • Publication number: 20040063325
    Abstract: In a semiconductor device having a MEMS according to this invention, a plurality of units having movable portions for constituting a MEMS are monolithically mounted on a semiconductor substrate on which an integrated circuit including a driving circuit, sensor circuit, memory, and processor is formed. Each unit has a processor, memory, driving circuit, and sensor circuit.
    Type: Application
    Filed: September 17, 2003
    Publication date: April 1, 2004
    Inventors: Masami Urano, Hiromu Ishii, Toshishige Shimamura, Yasuyuki Tanabe, Katsuyuki Machida, Tomomi Sakata
  • Patent number: 6624666
    Abstract: To achieve a differential type logic circuit operating at a high speed and with a low voltage, the circuit is composed of a differential push-pull circuit comprising enhancement type NMOSFETs and depletion type NMOSFETs and a CMOS inverter pair circuit comprising inverters, and a threshold voltage of FETs of the CMOS inverter pair circuit is set to a value same as or greater than a threshold voltage of enhancement type FETs of the differential push-pull circuit and smaller than about ½ of supply voltage.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: September 23, 2003
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Takakuni Douseki, Toshishige Shimamura
  • Publication number: 20030174934
    Abstract: An optical switch device includes at least an optical switch element and driving control circuit. In the optical switch element, a fixed electrode portion is arranged, via a dielectric layer, on a semiconductor substrate on which an integrated circuit is formed. A mirror structure has a plate-shaped movable portion arranged above the fixed electrode portion while opposing the fixed electrode portion. A reflecting portion is formed at least at part of the movable portion to reflect light. A support member is fixed around the fixed electrode portion on the semiconductor substrate via a dielectric layer and supports the mirror structure. The driving control circuit is incorporated in the integrated circuit to drive the optical switch element by applying a predetermined potential to the movable portion and fixed electrode portion.
    Type: Application
    Filed: March 11, 2003
    Publication date: September 18, 2003
    Inventors: Hiromu Ishii, Yasuyuki Tanabe, Katsuyuki Machida, Masami Urano, Toshishige Shimamura, Yuji Uenishi, Takanori Kiyokura
  • Patent number: 6556935
    Abstract: A small shape recognizing capacitive sensor device includes detection elements, sensor circuits, and a correction circuit. The detection elements are arranged adjacent to each other. The sensor circuits are connected to the detection elements, respectively. The correction circuit corrects the output signal level of the sensor circuit. The output signal level correction circuit includes a calibration circuit, calibration reference signal generation circuit, and comparison circuit. The calibration circuit is connected to the output side of the sensor circuit. The calibration reference signal generation circuit generates a calibration reference signal. The comparison circuit compares the output from the sensor circuit with the calibration reference signal and supplies the difference output to the calibration circuit as a control signal.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: April 29, 2003
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroki Morimura, Satoshi Shigematsu, Katsuyuki Machida, Hakaru Kyuragi, Toshishige Shimamura