Abstract: A calibration mode signal line to which sensor cells are commonly connected is arranged. In a calibration mode, a calibration mode signal is supplied to the sensor cells through the calibration mode signal line to designate calibration. In each sensor cell, when the calibration mode signal is being supplied from the calibration mode signal line, and the sensor cell is selected by the decoder, calibration operation of adjusting the detection sensitivity of a sensor circuit is executed using a calibration circuit.

Abstract: An image capturing apparatus includes an image capturing section and capture control section. The image capturing section converts the shape of an object into an electrical quantity in accordance with the parameter value set in a parameter setting section, and outputs image data representing an image corresponding to the shape of the object. The capture control section receives the image data output from the image capturing section, calculates an evaluation index for evaluating the image quality of the image from the image data. If the evaluation index falls outside the range of a preset reference value, the capture control section changes the parameter value set in the parameter setting section so as to make the evaluation index fall within the range of the reference value to output the image data which is received from the image capturing section and the evaluation index of which falls within the range of the reference value.

Abstract: A surface shape recognition sensor includes a plurality of capacitive detection elements, a support electrode, a protective film, and a plurality of projections. The capacitive detection elements are formed from lower electrodes and a deformable plate-like upper electrode made of a metal. The lower electrodes are insulated and isolated from each other and stationarily laid out on a single plane of an interlevel dielectric formed on a semiconductor substrate. The upper electrode is laid out above the lower electrodes at a predetermined interval and has a plurality of opening portions. The support electrode is laid out around the lower electrodes while being insulated and isolated from the lower electrodes, and formed to be higher than the lower electrodes to support the upper electrode. The protective film is formed on the upper electrode to close the opening portions. The projections are laid out in a region of the protective film above the capacitive detection element.

Abstract: An authentication token includes a personal collation unit and communication unit. The personal collation unit includes a sensor, storage unit, and collation unit. The sensor detects biometrical information of a user and outputs the detection result as sensing data. The storage unit stores in advance registered data to be collated with the biometrical information of the user. The collation unit collates the registered data with the sensing data and outputs the collation result as authentication data. The communication unit transmits the authentication data from the personal collation unit to the use device as communication data. The personal collation unit and communication unit are integrated.

Abstract: A small shape recognizing capacitive sensor device includes detection elements, sensor circuits, and a correction circuit. The detection elements are arranged adjacent to each other. The sensor circuits are connected to the detection elements, respectively. The correction circuit corrects the output signal level of the sensor circuit. The output signal level correction circuit includes a calibration circuit, calibration reference signal generation circuit, and comparison circuit. The calibration circuit is connected to the output side of the sensor circuit. The calibration reference signal generation circuit generates a calibration reference signal. The comparison circuit compares the output from the sensor circuit with the calibration reference signal and supplies the difference output to the calibration circuit as a control signal.

Abstract: To achieve a differential type logic circuit operating at a high speed and with a low voltage, the circuit is composed of a differential push-pull circuit comprising enhancement type NMOSFETs and depletion type NMOSFETs and a CMOS inverter pair circuit comprising inverters, and a threshold voltage of FETs of the CMOS inverter pair circuit is set to a value same as or greater than a threshold voltage of enhancement type FETs of the differential push-pull circuit and smaller than about ½ of supply voltage.