Patents by Inventor Toshiya Endo

Toshiya Endo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8441010
    Abstract: In a transistor including an oxide semiconductor, hydrogen in the oxide semiconductor leads to degradation of electric characteristics of the transistor. Thus, an object is to provide a semiconductor device having good electrical characteristics. An insulating layer in contact with an oxide semiconductor layer where a channel region is formed is formed by a plasma CVD method using a silicon halide. The insulating layer thus formed has a hydrogen concentration less than 6×1020 atoms/cm3 and a halogen concentration greater than or equal to 1×1020 atoms/cm3; accordingly, hydrogen diffusion into the oxide semiconductor layer can be prevented and hydrogen in the oxide semiconductor layer is inactivated or released from the oxide semiconductor layer by the halogen, whereby a semiconductor device having good electrical characteristics can be provided.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: May 14, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Toshiya Endo, Kunihiko Suzuki, Yasuhiko Takemura
  • Publication number: 20120319157
    Abstract: To provide a heterojunction photoelectric conversion device including passivation layers for reducing surface defects of a silicon substrate. The photoelectric conversion device includes a first silicon semiconductor layer which is in contact with one surface of a single crystal silicon substrate; a second silicon semiconductor layer which is in contact with the first silicon semiconductor layer; a third silicon semiconductor layer which is in contact with the other surface of the single crystal silicon substrate; and a fourth silicon semiconductor layer which is in contact with the third silicon semiconductor layer. Further, the fluorine concentration in the first silicon semiconductor layer and the third silicon semiconductor layer is lower than or equal to 1×1017 atoms/cm3.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 20, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mitsuhiro Ichuo, Toshiya Endo, Sho Kato
  • Publication number: 20120304932
    Abstract: An object of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus.
    Type: Application
    Filed: July 17, 2012
    Publication date: December 6, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Satoshi Toriumi, Ryota Tajima, Takashi Ohtsuki, Tetsuhiro Tanaka, Ryo Tokumaru, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi, Toshiya Endo, Shunpei Yamazaki
  • Patent number: 8252669
    Abstract: An object of one embodiment of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: August 28, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Ryota Tajima, Takashi Ohtsuki, Tetsuhiro Tanaka, Ryo Tokumaru, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi, Toshiya Endo, Shunpei Yamazaki
  • Publication number: 20120156556
    Abstract: An electrode in which a silicon layer is provided over a current collector, a thin film layer having a thickness within a certain range is provided on a surface of the silicon layer, and the thin film layer contains fluorine, is used for a power storage device. The thickness of the thin film layer containing fluorine is greater than 0 nm and less than or equal to 10 nm, preferably greater than or equal to 4 nm and less than or equal to 9 nm. The fluorine concentration of the thin film layer containing fluorine is preferably as high as possible, and the nitrogen concentration, the oxygen concentration, and the hydrogen concentration thereof are preferably as low as possible.
    Type: Application
    Filed: November 30, 2011
    Publication date: June 21, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazutaka KURIKI, Mitsuhiro Ichijo, Toshiya Endo
  • Publication number: 20120100677
    Abstract: A technique for manufacturing a microcrystalline semiconductor layer with high mass productivity is provided. In a reaction chamber of a plasma CVD apparatus, an upper electrode and a lower electrode are provided in almost parallel to each other. A hollow portion is formed in the upper electrode, and the upper electrode includes a shower plate having a plurality of holes formed on a surface of the upper electrode which faces the lower electrode. A substrate is provided over the lower electrode. A gas containing a deposition gas and hydrogen is supplied to the reaction chamber from the shower plate through the hollow portion of the upper electrode, and a rare gas is supplied to the reaction chamber from a portion different from the upper electrode. Accordingly, high-frequency power is supplied to the upper electrode to generate plasma, so that a microcrystalline semiconductor layer is formed over the substrate.
    Type: Application
    Filed: January 5, 2012
    Publication date: April 26, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mitsuhiro ICHIJO, Kazutaka KURIKI, Tomokazu YOKOI, Toshiya ENDO
  • Patent number: 8114760
    Abstract: A technique for manufacturing a microcrystalline semiconductor layer with high mass productivity is provided. In a reaction chamber of a plasma CVD apparatus, an upper electrode and a lower electrode are provided in almost parallel to each other. A hollow portion is formed in the upper electrode, and the upper electrode includes a shower plate having a plurality of holes formed on a surface of the upper electrode which faces the lower electrode. A substrate is provided over the lower electrode. A gas containing a deposition gas and hydrogen is supplied to the reaction chamber from the shower plate through the hollow portion of the upper electrode, and a rare gas is supplied to the reaction chamber from a portion different from the upper electrode. Accordingly, high-frequency power is supplied to the upper electrode to generate plasma, so that a microcrystalline semiconductor layer is formed over the substrate.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: February 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi, Toshiya Endo
  • Publication number: 20120001168
    Abstract: In a transistor including an oxide semiconductor, hydrogen in the oxide semiconductor leads to degradation of electric characteristics of the transistor. Thus, an object is to provide a semiconductor device having good electrical characteristics. An insulating layer in contact with an oxide semiconductor layer where a channel region is formed is formed by a plasma CVD method using a silicon halide. The insulating layer thus formed has a hydrogen concentration less than 6×1020 atoms/cm3 and a halogen concentration greater than or equal to 1×1020 atoms/cm3; accordingly, hydrogen diffusion into the oxide semiconductor layer can be prevented and hydrogen in the oxide semiconductor layer is inactivated or released from the oxide semiconductor layer by the halogen, whereby a semiconductor device having good electrical characteristics can be provided.
    Type: Application
    Filed: June 21, 2011
    Publication date: January 5, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mitsuhiro ICHIJO, Toshiya ENDO, Kunihiko SUZUKI, Yasuhiko TAKEMURA
  • Publication number: 20110309355
    Abstract: An object is to provide a semiconductor device having good electrical characteristics. A gate insulating layer having a hydrogen concentration less than 6×1020 atoms/cm3 and a fluorine concentration greater than or equal to 1×1020 atoms/cm3 is used as a gate insulating layer in contact with an oxide semiconductor layer forming a channel region, so that the amount of hydrogen released from the gate insulating layer can be reduced and diffusion of hydrogen into the oxide semiconductor layer can be prevented. Further, hydrogen present in the oxide semiconductor layer can be eliminated with the use of fluorine; thus, the hydrogen content in the oxide semiconductor layer can be reduced. Consequently, the semiconductor device having good electrical characteristics can be provided.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 22, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mitsuhiro ICHIJO, Toshiya ENDO, Kunihiko SUZUKI
  • Publication number: 20110284959
    Abstract: One object is to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. Another object is to manufacture a highly reliable semiconductor device in a high yield. In a top-gate staggered transistor including an oxide semiconductor film, as a first gate insulating film in contact with the oxide semiconductor film, a silicon oxide film is formed by a plasma CVD method with use of a deposition gas containing silicon fluoride and oxygen; and as a second gate insulating film stacked over the first gate insulating film, a silicon oxide film is formed by a plasma CVD method with use of a deposition gas containing silicon hydride and oxygen.
    Type: Application
    Filed: May 3, 2011
    Publication date: November 24, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kunio KIMURA, Mitsuhiro ICHIJO, Toshiya ENDO
  • Publication number: 20110284854
    Abstract: In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which forms a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×1020 atoms/cm3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 24, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuta ENDO, Toshinari SASAKI, Kosei NODA, Mizuho SATO, Mitsuhiro ICHIJO, Toshiya ENDO
  • Publication number: 20110097877
    Abstract: A technique for manufacturing a microcrystalline semiconductor layer with high mass productivity is provided. In a reaction chamber of a plasma CVD apparatus, an upper electrode and a lower electrode are provided in almost parallel to each other. A hollow portion is formed in the upper electrode, and the upper electrode includes a shower plate having a plurality of holes formed on a surface of the upper electrode which faces the lower electrode. A substrate is provided over the lower electrode. A gas containing a deposition gas and hydrogen is supplied to the reaction chamber from the shower plate through the hollow portion of the upper electrode, and a rare gas is supplied to the reaction chamber from a portion different from the upper electrode. Accordingly, high-frequency power is supplied to the upper electrode to generate plasma, so that a microcrystalline semiconductor layer is formed over the substrate.
    Type: Application
    Filed: October 20, 2010
    Publication date: April 28, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mitsuhiro ICHIJO, Kazutaka KURIKI, Tomokazu YOKOI, Toshiya ENDO
  • Publication number: 20110053358
    Abstract: An object of one embodiment of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus.
    Type: Application
    Filed: August 20, 2010
    Publication date: March 3, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Satoshi TORIUMI, Ryota TAJIMA, Takashi OHTSUKI, Tetsuhiro TANAKA, Ryo TOKUMARU, Mitsuhiro ICHIJO, Kazutaka KURIKI, Tomokazu YOKOI, Toshiya ENDO, Shunpei YAMAZAKI
  • Publication number: 20100139766
    Abstract: A highly-efficient photoelectric conversion device is provided without complicating the manufacturing process. The photoelectric conversion device includes a unit cell having a semiconductor junction, in which a first impurity semiconductor layer having one conductivity type, a semiconductor layer including a first semiconductor region having a larger proportion of a crystalline semiconductor than an amorphous semiconductor and a second semiconductor region having a larger proportion of an amorphous semiconductor than a crystalline semiconductor and including both a radial crystal and a crystal having a needle-like growing end in the amorphous semiconductor, and a second impurity semiconductor layer having a conductivity type opposite to the conductivity type of the first impurity semiconductor layer are stacked in this order.
    Type: Application
    Filed: November 23, 2009
    Publication date: June 10, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Satoshi TORIUMI, Toshiya ENDO, Eriko OHMORI
  • Patent number: 6930724
    Abstract: Light from an object is incident to an image sensing device and converted into an image signal. The image sensing device is exposed to the light by a shutter, provided between the object and the solid-state image sensing device, for a first exposure period and a second exposure period that directly follows the first exposure period. The first and the second periods are the same length in time. Each exposure period for exposing the solid-state image sensing device to the light corresponds to one frame or one filed of the object. A passage of the light that has passed the shutter and incident to the solid-state image sensing device is shifted in a predetermined direction with respect to the solid-state image sensing device at least in the second exposure period. Image signals converted for the first and the second exposure periods are combined to generate a composite image signal.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: August 16, 2005
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Hideki Tengeiji, Toshiya Endo, Yoshichi Otake
  • Patent number: 5017443
    Abstract: In a battery housing device including a case for receiving at least two batteries in a parallel condition, retaining means provided in the vicinity of one of inside surfaces of the case, and an electrode spring adapted to be retained by the retaining means, wherein positive and negative electrodes of the batteries are electrically connected to each other through the electrode spring.
    Type: Grant
    Filed: July 28, 1989
    Date of Patent: May 21, 1991
    Assignee: Alps Electric Co., Ltd.
    Inventors: Tomohisa Tominaga, Kazuichi Sato, Kouichi Otsuka, Toshiya Endo, Susumu Oikawa
  • Patent number: 4655734
    Abstract: An endless belt for the power transmission, wherein a plurality of block bodies each comprising a body member formed of a highly rigid material and provided at opposite side portions thereof with inclined surfaces being in frictional engagement with pulleys and a clamp member formed separately of said body member are arranged in a row and adjacent to one another on a belt-shaped endless carrier formed of fabric in such a manner that the endless carrier is clamped between the body members and the clamp members, the endless belt being of such an arrangement that the belt-shaped endless carrier formed of fabric is woven by warps disposed in the longitudinal direction and wefts disposed in the widthwise direction, with the wefts restraining the warps.
    Type: Grant
    Filed: July 1, 1985
    Date of Patent: April 7, 1987
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Susumu Okawa, Yasunobu Jufuku, Shigeru Okuwaki, Takayoshi Kondou, Toshiya Endo, Shigenori Nakata