Patents by Inventor Toshiya Kotani

Toshiya Kotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7506301
    Abstract: A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: March 17, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
  • Patent number: 7499582
    Abstract: There is disclosed a method for inspecting a defect in a photomask which is produced by using a graphic data, that matches mask data or is produced by subjecting mask data to correction of a process conversion difference relating to at least a line width. The method includes the following steps. Inspection data is produced by correcting a pattern of mask data so as to substantially match a planar shape of a pattern of a photomask to be produced by using the graphic data. A pattern of a produced photomask is compared with a pattern of the inspection data. Portions where planar shapes of the pattern of the inspection data and the pattern of the produced photomask do not match are extracted. A defect is distinguished from the portions where the planer shapes do not match.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: March 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Suigen Kyoh, Shinji Yamaguchi, Soichi Inoue
  • Patent number: 7482661
    Abstract: A pattern forming method includes determining an allowable value of an etching conversion difference, obtaining a maximum distance between patterns generating the etching conversion difference within the allowable value, the patterns including main patterns or both main patterns and a dummy pattern, preparing a first design layout in which a first distance between the main patterns is smaller than the maximum distance, or a second design layout in which a second distance between the main patterns and the dummy pattern is smaller than the maximum distance, performing a design data conversion based on the first or second design layout to form first or second design data, and forming the main patterns by using the first design data, or forming both the main patterns and the dummy pattern by using the second design data.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: January 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Satoshi Tanaka, Soichi Inoue
  • Patent number: 7483155
    Abstract: Wavelength dispersion of intensity of light reflected from an evaluation object is measured. A complex refractive index of a substance forming the evaluation object and the environment are prepared. Virtual component ratios comprising a mixture ratio of the substances forming the evaluation object and the environment are prepared. Reflectance wavelength dispersions to the virtual component ratios are calculated. Similar reflectance wavelength dispersions having a small difference with the measured wavelength dispersion are extracted from the reflectance wavelength dispersions. Weighted average to the virtual component ratios used for calculating the similar reflectance wavelength dispersions are calculated to obtain a component ratio of the substance forming the evaluation object and the environment so that weighting is larger when the difference is smaller. A structure of the evaluation object is determined from the calculated component ratio.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: January 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Hayasaki, Toru Mikami, Shinichi Ito, Yuichiro Yamazaki, Toshiya Kotani
  • Publication number: 20090019418
    Abstract: A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the pattern by calculation of an intensity of the energy ray; locally changing, at least in a portion corresponding to a pattern to be interested, a relative position in a direction of the intensity of the energy ray between a latent image curve and a reference intensity line in accordance with a distance between the pattern to be interested and a pattern of a neighboring region, the latent image curve being an intensity distribution curve of the energy ray constituting the latent image, the reference intensity line being defined to specify a position of an edge of the pattern to be interested; and calculating a distance between intersections of a portion of the latent image curve corresponding to the pattern to be interested and the referenc
    Type: Application
    Filed: August 11, 2008
    Publication date: January 15, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi
  • Publication number: 20090014841
    Abstract: A first region having a first pattern which includes a first minimum dimension, a second region having a second pattern which includes a second minimum dimension larger the first minimum dimension, the second region being arranged adjacent to the first region, wherein a boundary between the first region and the second region is sectioned by a width which is twice of more of a minimum dimension which exists in an adjacent region.
    Type: Application
    Filed: July 8, 2008
    Publication date: January 15, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kosuke YANAGIDAIRA, Takuya Futatsuyama, Toshiya Kotani
  • Publication number: 20090011370
    Abstract: A pattern forming method using two layers of resist pattern stacked one on the other has been disclosed. First, a first resist pattern is formed on a to-be-processed film. The first resist pattern is slimmed. On the slimmed first resist pattern and to-be-processed film, a second resist pattern is formed. With the first and second resist patterns as a mask, the film is processed.
    Type: Application
    Filed: June 10, 2008
    Publication date: January 8, 2009
    Inventors: Hiroko Nakamura, Koji Hashimoto, Soichi Inoue, Toshiya Kotani
  • Publication number: 20080320434
    Abstract: A photomask is washed and at least one physical amount of transmittance and phase difference of the photomask, dimension of a pattern, height of the pattern and a sidewall shape of the pattern is measured. After this, the two-dimensional shape of a borderline pattern previously determined for the photomask is measured. Lithography tolerance is derived by performing a lithography simulation for the measured two-dimensional shape by use of the measured physical amount. Then, whether the photomask can be used or not is determined based on the derived lithography tolerance.
    Type: Application
    Filed: April 30, 2008
    Publication date: December 25, 2008
    Inventors: Hidefumi MUKAI, Shinji Yamaguchi, Yukiyasu Arisawa, Toshiya Kotani
  • Publication number: 20080301621
    Abstract: In a model-based OPC which makes a suitable mask correction for each mask pattern using an optical image intensity simulator, a mask pattern is divided into subregions and the model of optical image intensity simulation is changed according to the contents of the pattern in each subregion. When the minimum dimensions of the mask pattern are smaller than a specific threshold value set near the exposure wavelength, the region is calculated using a high-accuracy model and the other regions are calculated using a high-speed model.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 4, 2008
    Inventors: Kazuya FUKUHARA, Tatsuhiko HIGASHIKI, Toshiya KOTANI, Satoshi TANAKA, Takashi SATO, Akiko MIMOTOGI, Masaki SATAKE
  • Patent number: 7458057
    Abstract: According to an aspect of the invention, there is provided a pattern correction method in which a shape of a target pattern is corrected in accordance with an arrangement state between the target pattern configuring a designed pattern and a vicinity pattern disposed in the vicinity of the target pattern, the pattern correction method comprises detecting a first arrangement state between a first predetermined portion of an edge of the target pattern and the vicinity pattern, detecting a second arrangement state between a second predetermined portion of the edge of the target pattern and the vicinity pattern, determining a correction value of the edge of the target pattern based on a rule in accordance with the first and second arrangement states, and adding the correction value to the edge of the target pattern.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: November 25, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiya Kotani
  • Publication number: 20080276216
    Abstract: A pattern forming method of forming a desired pattern on a semiconductor substrate is disclosed, which comprises extracting a first pattern of a layer, extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern, calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation, determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns, and correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin.
    Type: Application
    Filed: July 1, 2008
    Publication date: November 6, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ayako Nakano, Toshiya Kotani
  • Publication number: 20080250381
    Abstract: A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined permissible variation and defining the adjusted parameter as a reference parameter of the reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate using the reference manufacturing device from a mask to form the pattern on the substrate when the reference parameter is set to the reference manufacturing device and defining the obtained first shape as a reference finished shape; defining an adjustable parameter of another to-be-adjusted manufacturing device as a to-be-adjusted parameter of the to-be-adjusted manufacturing device; obtaining a second shape of the pattern formed on the substrate using the to-be-adjusted manufacturi
    Type: Application
    Filed: April 4, 2008
    Publication date: October 9, 2008
    Inventors: Toshiya KOTANI, Yasunobu Kai, Soichi Inoue, Satoshi Tanaka, Shigeki Nojima, Kazuyuki Masukawa, Koji Hashimoto
  • Publication number: 20080235650
    Abstract: A pattern creation method, including laying out data of a most extreme end pattern of integrated circuit patterns on a first layer and laying out data of the integrated circuit patterns excluding the most extreme end pattern on a second layer, extracting data of a first most proximate pattern being most proximate to the most extreme end pattern from the second layer and converting the extracted data to a third layer, generating data of a contacting pattern which contacts both the first most proximate pattern and the most extreme end pattern in a fourth layer, generating data of a non-overlapping pattern of the contacting pattern excluding overlapping portions with the most extreme end pattern and the first most proximate pattern in a fifth layer, extracting data of a second most proximate pattern being most proximate to the non-overlapping pattern and converting the extracted data to the first layer.
    Type: Application
    Filed: March 18, 2008
    Publication date: September 25, 2008
    Inventors: Takeshi Ito, Satoshi Tanaka, Toshiya Kotani, Tadahito Fujisawa, Koji Hashimoto
  • Patent number: 7426712
    Abstract: A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the pattern by calculation of an intensity of the energy ray; locally changing, at least in a portion corresponding to a pattern of interest, a relative position in a direction of the intensity of the energy ray between a latent image curve and a reference intensity line in accordance with a distance between the pattern of interest and a pattern of a neighboring region , the latent image curve being an intensity distribution curve of the energy ray constituting the latent image, the reference intensity line being defined to specify a position of an edge of the pattern of interest; and calculating a distance between intersections of a portion of the latent image curve corresponding to the pattern of interest and the reference intensity line in
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: September 16, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi
  • Publication number: 20080216045
    Abstract: Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.
    Type: Application
    Filed: November 27, 2007
    Publication date: September 4, 2008
    Inventors: Sachiko KOBAYASHI, Toshiya Kotani, Shinichiroh Ohki, Hirotaka Ichikawa
  • Patent number: 7402363
    Abstract: A pattern forming method of forming a desired pattern on a semiconductor substrate is disclosed, which comprises extracting a first pattern of a layer, extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern, calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation, determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns, and correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: July 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ayako Nakano, Toshiya Kotani
  • Patent number: 7370314
    Abstract: A method for generating layout data of a semiconductor integrated circuit includes applying optical proximity correction conditions to cells so as to generate cell patterns, selecting cell patterns to correspond cells, based on layout information of cells along a specified signal propagating path; calculating delay times for the signal propagating path for combinations of cell patterns; selecting a combination of cell patterns, based on lengths of the calculated delay times and the allowable delay time; and generating layout data of the signal propagating path using the selected combination.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: May 6, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumihiro Minami, Toshiya Kotani
  • Publication number: 20080070402
    Abstract: A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on the block film and insulating layer. Etching is performed by using the resist film as a mask, thereby forming the first hole in the block film and insulating layer, and the second hole in the insulating layer. The depth of the first hole from the upper surface of the insulating layer is smaller than that of the second hole, so the first hole does not reach the semiconductor substrate.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 20, 2008
    Inventors: Toshiya Kotani, Hiroko Nakamura, Koji Hashimoto
  • Patent number: 7337426
    Abstract: There is disclosed a pattern correcting method comprising extracting a correction pattern, at least the one or more correction patterns being included in a first design pattern formed on a substrate, acquiring layout information from the first design pattern, the layout information affecting a finished plane shape of the correction pattern on the substrate, determining contents of correction onto the correction pattern on the basis of the layout information, generating a design pattern-2 corresponding to the layout information so as to be associated with the correction pattern, and correcting the correction pattern in accordance with the contents of correction corresponding to the design pattern-2.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: February 26, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Shigeki Nojima, Kazuhito Kobayashi
  • Publication number: 20070226676
    Abstract: A method in which a desired pattern is compared with a finish pattern to be formed on a wafer, which is predicted from a design pattern, based on a calculation of a light beam intensity, and a deviation quantity of the finish pattern from the desired pattern at each edge of the finish pattern and the desired pattern is calculated, comprising setting a reference light beam intensity for setting the desired pattern on a wafer, setting an evaluation point for comparison of the finish pattern with the desired pattern, calculating a light beam intensity at the evaluation point, calculating a differentiation value of the light beam intensity at the evaluation point, calculating an intersection of the differentiation value with the reference light beam intensity, and calculating a difference between the intersection and the evaluation point, the difference defining an edge deviation quantity of the finish pattern from the desired pattern.
    Type: Application
    Filed: March 26, 2007
    Publication date: September 27, 2007
    Inventors: Kyoko Izuha, Toshiya Kotani, Satoshi Tanaka