Patents by Inventor Toshiya Kotani

Toshiya Kotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20100202181
    Abstract: A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on three or more rows. The center of each of two of the interconnect contacts which are connected to the interconnects adjacent in the second direction deviate from each other along the first direction.
    Type: Application
    Filed: September 17, 2009
    Publication date: August 12, 2010
    Inventors: Takaki HASHIMOTO, Hidefumi Mukai, Yasunobu Kai, Toshiya Kotani
  • Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device
    Publication number: 20100193960
    Abstract: A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (?2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern N1 and at least one circuit pattern Ni (i?2) arranged in one direction different from longitudinal direction of the circuit pattern N1, the at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.
    Type: Application
    Filed: March 22, 2010
    Publication date: August 5, 2010
    Inventors: Hiromitsu Mashita, Toshiya Kotani, Atsushi Maesono, Ayako Nakano, Tadahito Fujisawa
  • Semiconductor device pattern creation method, pattern data processing program, and semiconductor device manufacturing method
    Patent number: 7770145
    Abstract: A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: August 3, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ayako Nakano, Satoshi Tanaka, Toshiya Kotani
  • PATTERN GENERATING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, COMPUTER PROGRAM PRODUCT, AND PATTERN-SHAPE-DETERMINATION-PARAMETER GENERATING METHOD
    Publication number: 20100190342
    Abstract: A pattern generating method includes: extracting, from a shape of a pattern generated on a substrate, a contour of the pattern shape; setting evaluation points as verification points for the pattern shape on the contour; calculating curvatures on the contour in the evaluation points; and verifying the pattern shape based on whether the curvatures satisfy a predetermined threshold set in advance.
    Type: Application
    Filed: January 7, 2010
    Publication date: July 29, 2010
    Inventors: Toshiya Kotani, Hiromitsu Mashita, Takafumi Taguchi, Ryuji Ogawa
  • PATTERN DATA CREATING METHOD, COMPUTER PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
    Publication number: 20100185313
    Abstract: A pattern data creating method comprising: referring to a first correspondence relation between an amount of dimension variation between a first pattern formed on a substrate and a second pattern formed by processing the substrate using the first pattern and either one of a pattern total surface area and a pattern boundary length of the first pattern; and creating pattern data for forming the first pattern.
    Type: Application
    Filed: January 15, 2010
    Publication date: July 22, 2010
    Inventors: Hiromitsu MASHITA, Katsumi Iyanagi, Takafumi Taguchi, Toshiya Kotani, Hidefumi Mukai, Taiga Uno, Takashi Nakazawa
  • MASK VERIFICATION METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER READABLE MEDIUM
    Publication number: 20100168895
    Abstract: A mask verification method includes setting optical parameters, verifying whether a pattern, which is obtained when a mask pattern other than a reference pattern of patterns on a mask is transferred on a substrate with use of the set optical parameters, satisfies dimensional specifications, and varying, when the pattern which is obtained when the mask pattern is transferred on the substrate is determined to fail to satisfy the dimensional specifications, the optical parameters at the time of transfer such that the pattern, which is obtained when the reference pattern is transferred on the substrate, satisfies a target dimensional condition, and verifying whether a pattern, which is obtained when the mask pattern other than the reference pattern of the patterns on the mask is transferred on the substrate with use of the varied optical parameters, satisfies the dimensional specifications.
    Type: Application
    Filed: September 17, 2009
    Publication date: July 1, 2010
    Inventors: Hiromitsu MASHITA, Fumiharu Nakajima, Toshiya Kotani, Hidefumi Mukai, Issui Aiba
  • MASK PATTERN CORRECTING METHOD, MASK PATTERN INSPECTING METHOD, PHOTO MASK MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
    Publication number: 20100159709
    Abstract: A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
    Type: Application
    Filed: March 4, 2010
    Publication date: June 24, 2010
    Inventors: Toshiya KOTANI, Satoshi Tanaka, Shigeki Nojima, Koji Hashimoto, Soichi Inoue
  • Semiconductor device and method for manufacturing
    Patent number: 7738276
    Abstract: A first region having a first pattern which includes a first minimum dimension, a second region having a second pattern which includes a second minimum dimension larger the first minimum dimension, the second region being arranged adjacent to the first region, wherein a boundary between the first region and the second region is sectioned by a width which is twice of more of a minimum dimension which exists in an adjacent region.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Yanagidaira, Takuya Futatsuyama, Toshiya Kotani
  • System, method and program for generating mask data, exposure mask and semiconductor device in consideration of optical proximity effects
    Patent number: 7716628
    Abstract: A system for generating mask data includes an extracting module extracting a block necessary to correct process proximity effects as a wide correction area from a plurality of blocks by comparing parameter, a wide correction data generator generating wide correction data to make the correction applied to the wide correction area, and a mask data generator generating mask data by applying the wide correction data to the wide correction area.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: May 11, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Tanaka, Kazuya Fukuhara, Toshiya Kotani
  • Method for manufacturing semiconductor device
    Patent number: 7713833
    Abstract: According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: May 11, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiromitsu Mashita, Toshiya Kotani, Hidefumi Mukai, Fumiharu Nakajima, Chikaaki Kodama
  • Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device
    Patent number: 7716617
    Abstract: A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (?2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern N1 and at least one circuit pattern Ni (i?2) arranged in one direction different from longitudinal direction of the circuit pattern N1, the at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: May 11, 2010
    Assignee: Kabushiki Kaisha Tosbhia
    Inventors: Hiromitsu Mashita, Toshiya Kotani, Atsushi Maesono, Ayako Nakano, Tadahito Fujisawa
  • Semiconductor memory device
    Patent number: 7700997
    Abstract: According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; and electrical connections for connection said word lines and sources or drains of said first transistors, said electrical connections being formed of both first wirings of a first wiring layer formed above said first gate wiring layer and second wirings of a second wiring layers formed above said first wiring layer.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: April 20, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuya Futatsuyama, Toshiya Kotani, Hiromitsu Mashita, Atsushi Maesono, Ayako Nakano, Tadahito Fujisawa
  • METHOD OF CALCULATING PATTERN-FAILURE-OCCURRENCE-REGION, COMPUTER PROGRAM PRODUCT, PATTERN-LAYOUT EVALUATING METHOD, AND SEMICONDUCTOR-DEVICE MANUFACTURING METHOD
    Publication number: 20100082144
    Abstract: Method of calculating pattern-failure-occurrence-region comprising calculating a pattern failure occurrence region using relation information and a layout used for forming a convex section, the relation information being a relation between a distance from a formed pattern in a film to cover the convex section on a substrate to the convex section and a region in the film in which a shape of the formed pattern cannot satisfy a predetermined condition because of influence of the convex section.
    Type: Application
    Filed: September 4, 2009
    Publication date: April 1, 2010
    Inventors: Masanori TAKAHASHI, Toshiya Kotani, Satoshi Tanaka
  • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20100081265
    Abstract: According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.
    Type: Application
    Filed: September 10, 2009
    Publication date: April 1, 2010
    Inventors: Hiromitsu Mashita, Toshiya Kotani, Hidefumi Mukai, Fumiharu Nakajima, Chikaaki Kodama
  • Pattern creation method, mask manufacturing method and semiconductor device manufacturing method
    Patent number: 7669172
    Abstract: A pattern creation method, including laying out data of a most extreme end pattern of integrated circuit patterns on a first layer and laying out data of the integrated circuit patterns excluding the most extreme end pattern on a second layer, extracting data of a first most proximate pattern being most proximate to the most extreme end pattern from the second layer and converting the extracted data to a third layer, generating data of a contacting pattern which contacts both the first most proximate pattern and the most extreme end pattern in a fourth layer, generating data of a non-overlapping pattern of the contacting pattern excluding overlapping portions with the most extreme end pattern and the first most proximate pattern in a fifth layer, extracting data of a second most proximate pattern being most proximate to the non-overlapping pattern and converting the extracted data to the first layer.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: February 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Ito, Satoshi Tanaka, Toshiya Kotani, Tadahito Fujisawa, Koji Hashimoto
  • METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    Publication number: 20100038795
    Abstract: A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.
    Type: Application
    Filed: August 17, 2009
    Publication date: February 18, 2010
    Inventors: Ryota Aburada, Hiromitsu Mashita, Toshiya Kotani, Chikaaki Kodama
  • PATTERN PREDICTING METHOD, RECORDING MEDIA AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20100035168
    Abstract: A pattern predicting method according to one embodiment includes obtaining shape data of a target pattern from shape data of a second pattern to be formed by transferring a first pattern at predetermined process conditions by using a first neutral network, the target pattern being to be a target of the second pattern when the first pattern is transferred at the predetermined process conditions, so as to keep the transferred patterns within an acceptable range, the transferred patterns being formed by transferring the first pattern at process conditions changed from the predetermined process conditions and obtaining shape data of a new first pattern for forming the target pattern at the predetermined process conditions by using a second neutral network.
    Type: Application
    Filed: August 7, 2009
    Publication date: February 11, 2010
    Inventors: Fumiharu NAKAJIMA, Toshiya Kotani, Hiromitsu Mashita, Chikaaki Kodama
  • PATTERN SHAPE PREDICTING METHOD AND PATTERN SHAPE PREDICTING APPARATUS
    Publication number: 20100030545
    Abstract: A pattern shape predicting method comprising: predicting, with simulation, an intensity distribution of a pattern image concerning a pattern shape of a pattern on substrate formed on a substrate based on pattern data; calculating a first pattern edge position from the intensity distribution of the pattern image; calculating a feature value of the intensity distribution of the pattern image in a predetermined range including the first pattern edge position; calculating a fluctuation amount of the first pattern edge position from the feature value using a correlation; and predicting a second pattern edge position taking into account the fluctuation amount with respect to the first pattern edge position.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 4, 2010
    Inventors: Taiga UNO, Toshiya Kotani
  • MASK PATTERN DATA CREATION METHOD AND MASK
    Publication number: 20100021825
    Abstract: A mask pattern data creation method includes: determining whether or not a spacing of adjacent assist pattern feature data is not more than a prescribed spacing, based on: initial position data indicating an initially set position of the assist pattern feature data determined based on an illumination condition; and initial size data indicating an initially set size of the assist pattern feature data satisfying a size condition to not optically form an image on the transfer destination; and moving at least one of the adjacent assist pattern feature data or reducing a size of the at least one to increase the spacing of the assist pattern feature data to exceed a prescribed spacing in the case where it is determined that the spacing of the assist pattern feature data is not more than the prescribed spacing.
    Type: Application
    Filed: June 4, 2009
    Publication date: January 28, 2010
    Inventors: Chikaaki KODAMA, Hirotaka Ichikawa, Kazuyuki Masukawa, Toshiya Kotani
  • DESIGN LAYOUT DATA CREATING METHOD, COMPUTER PROGRAM PRODUCT, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20100003819
    Abstract: A design layout data creating method includes creating design layout data of a semiconductor device such that patterns formed on a wafer when patterns corresponding to the design layout data are formed on the wafer have a pattern coverage ratio within a predetermined range in a wafer surface and total peripheral length of the patterns formed on the wafer when the patterns corresponding to the design layout are formed on the wafer is pattern peripheral length within a predetermined range.
    Type: Application
    Filed: June 24, 2009
    Publication date: January 7, 2010
    Inventors: Takafumi TAGUCHI, Toshiya KOTANI, Hiromitsu MASHITA, Fumiharu NAKAJIMA, Chikaaki KODAMA