Patents by Inventor Toshiya Shimizu

Toshiya Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230222385
    Abstract: An evaluation method executed by a computer, the evaluation method comprising processing of: generating, based on information that indicates a degree of reduction of inference accuracy of a machine learning model to a change in first training data, second training data that reduces the inference accuracy; training the machine learning model by using the second training data; and evaluating the trained machine learning model.
    Type: Application
    Filed: February 27, 2023
    Publication date: July 13, 2023
    Applicant: FUJITSU LIMITED
    Inventors: Toshiya SHIMIZU, Yuji HIGUCHI
  • Publication number: 20230075524
    Abstract: A signature control method implemented by a computer, the signature control method including: acquiring, by a processor circuit of the computer, a plurality of pieces of document information and signature information that corresponds to each piece of document information of the plurality of pieces of document information; generating, by the processor circuit of the computer, aggregate signature information obtained by aggregating the signature information that corresponds to the each piece of document information of the plurality of acquired pieces of document information on a basis of the plurality of acquired pieces of document information; and outputting, by the processor circuit of the computer, the generated aggregate signature information in association with aggregate public key information obtained by aggregating public key information that corresponds to the each piece of document information of the plurality of pieces of document information and the plurality of pieces of document information.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 9, 2023
    Applicant: FUJITSU LIMITED
    Inventors: Rikuhiro Kojima, Dai YAMAMOTO, KOICHI YASAKI, Jumpei Yamaguchi, Toshiya Shimizu
  • Publication number: 20230009999
    Abstract: A recording medium storing a program causing a computer to execute: acquiring, for each model, an attack result of an estimation attack, the acquiring for a respective model being performed by using the respective model and a plurality of data, each model being a model trained by using synthetic data that simulates training data, an amount of the synthetic data for each model being different from each other; specifying, based on the attack result for each model, specific data from among the plurality of data; performing the estimation attack by using the specific data for a specific model of which an amount of the synthetic data is between the amounts of the synthetic data used for any two models; and evaluating, based on an attack result for the specific data and the attack result for each model, a resistance to the estimation attack for the specific model.
    Type: Application
    Filed: April 25, 2022
    Publication date: January 12, 2023
    Applicant: FUJITSU LIMITED
    Inventors: Yuji Higuchi, Ikuya Morikawa, Toshiya Shimizu
  • Publication number: 20220301288
    Abstract: A storage unit holds a classification model that calculates a confidence score from image data, and a transformation model that is a model for transforming a feature value having fewer dimensions than the image data into the image data and is created such that a set of feature values corresponding to a set of image data follows a probability distribution. A processing unit extracts a feature value according to the probability distribution. The processing unit transforms the feature value into image data using the transformation model and calculates a confidence score corresponding to the image data using the classification model. The processing unit updates, based on the probability distribution and the feature value, a feature value to be input to the transformation model from the feature value to a feature value in such a manner that a confidence score to be calculated is higher than the confidence score.
    Type: Application
    Filed: June 1, 2022
    Publication date: September 22, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Yuji Higuchi, Toshiya Shimizu, Ikuya Morikawa
  • Publication number: 20220277174
    Abstract: An evaluation method performed by a computer, the evaluation method includes generating a plurality of subsets that contain one or more pieces of training data, based on a set of a plurality of pieces of training data that includes pairs of input data and labels for machine learning, generating a trained model configured to estimate the labels from the input data, for each of the subsets, by performing the machine learning that uses the training data contained in the subsets, and performing evaluation related to aggression to the machine learning in the training data contained in the subsets, for each of the subsets, based on estimation accuracy of the trained model generated by using the training data contained in the subsets.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 1, 2022
    Applicant: FUJITSU LIMITED
    Inventor: Toshiya Shimizu
  • Patent number: 11431489
    Abstract: An encryption processing system includes: a first device; second devices; and a third device, wherein the first device generates synthesis keys by selecting public keys of the second devices; generates an intermediate text from confidential texts generated by encrypting secret information by using public keys of the second devices having decryption authority; generates ciphertexts by further encrypting the intermediate text using the synthesis keys; and makes public the ciphertexts, each of the second devices verifies validity of the ciphertexts; generates decryption key fragments by using an own private key; and makes public the decryption key fragments, the third device verifies validity of the decryption key fragments; generates a decryption key by combining decryption key fragments; generates the Intermediate text by decrypting one of the ciphertexts; and makes public the intermediate text, and the second device decrypts the intermediate text using the own private key; and restores the secret information.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: August 30, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Toshiya Shimizu, Takeshi Shimoyama, Goichiro Hanaoka, Yusuke Sakai, Seonghan Shin
  • Publication number: 20220222336
    Abstract: A non-transitory computer-readable recording medium storing an information processing program for causing a computer to execute processing, the processing including: generating a trigger image by using a generation processing configured to receive an input image and output the trigger image; calculating a first index that determines whether or not the trigger image serves as a backdoor for a trained target model; calculating a second index that determines whether or not the trigger image is included in an image set prepared in advance as prior knowledge; executing machine learning of the generation processing using the first index and the second index; and detecting a backdoor that exists in the target model on a basis of the first index for the trigger image generated by the generation processing in which the machine learning has been executed.
    Type: Application
    Filed: November 1, 2021
    Publication date: July 14, 2022
    Applicant: FUJITSU LIMITED
    Inventor: Toshiya Shimizu
  • Publication number: 20220215386
    Abstract: A transaction management device includes: a memory; and a processor coupled to the memory. The processor is configured to register, into a database, with respect to a first blockchain that stores a plurality of transactions with which first information and second information are associated, a plurality of multiple pieces of the second information in the plurality of transactions in units of groups based on the first information; and register, into a second blockchain, hash values obtained by hashing the plurality of pieces of second information in the units cf groups.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Yuki Yonekura, Toshiya Shimizu, Shingo Fujimoto
  • Patent number: 11163532
    Abstract: A method may include obtaining a set of multivariate quadratic polynomials associated with a multivariate quadratic problem and generating an Ising Model connection weight matrix “W” and an Ising Model bias vector “b” based on the multivariate quadratic polynomials. The method may also include providing the matrix “W” and the vector “b” to an annealing system configured to solve problems written according to the Ising Model and obtaining an output from the annealing system that represents a set of integers. The method may also include using the set of integers as a solution to the multivariate quadratic problem.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: November 2, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Hart Montgomery, Arnab Roy, Ryuichi Ohori, Toshiya Shimizu, Takeshi Shimoyama, Jumpei Yamaguchi
  • Publication number: 20210232958
    Abstract: A non-transitory computer-readable storage medium storing a program that causes a processor included in a computer to execute a process, the process includes calculating, by using a tolerance being predetermined and information on a Hamiltonian, a half adjust position with which an error of the Hamiltonian between a numerical value of the Hamiltonian before approximation of the Hamiltonian and the numerical value of the Hamiltonian after the approximation of the Hamiltonian is smaller than or equal to the tolerance, and performing integerization on the numerical value of the Hamiltonian based on the half adjust position.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 29, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Jumpei Yamaguchi, Toshiya Shimizu, Ryuichi Ohori
  • Publication number: 20210135851
    Abstract: An encryption processing system includes: a first device; second devices; and a third device, wherein the first device generates synthesis keys by selecting public keys of the second devices; generates an intermediate text from confidential texts generated by encrypting secret information by using public keys of the second devices having decryption authority; generates ciphertexts by further encrypting the intermediate text using the synthesis keys; and makes public the ciphertexts, each of the second devices verifies validity of the ciphertexts; generates decryption key fragments by using an own private key; and makes public the decryption key fragments, the third device verifies validity of the decryption key fragments; generates a decryption key by combining decryption key fragments; generates the Intermediate text by decrypting one of the ciphertexts; and makes public the intermediate text, and the second device decrypts the intermediate text using the own private key; and restores the secret information.
    Type: Application
    Filed: October 27, 2020
    Publication date: May 6, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Toshiya Shimizu, Takeshi SHIMOYAMA, Goichiro Hanaoka, Yusuke Sakai, Seonghan Shin
  • Publication number: 20200233643
    Abstract: A method may include obtaining a set of multivariate quadratic polynomials associated with a multivariate quadratic problem and generating an Ising Model connection weight matrix “W and an Ising Model bias vector “b” based on the multivariate quadratic polynomials. The method may also include providing the matrix “W” and the vector “b” to an annealing system configured to solve problems written according to the Ising Model and obtaining an output from the annealing system that represents a set of integers. The method may also include using the set of integers as a solution to the multivariate quadratic problem.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 23, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Hart MONTGOMERY, Arnab ROY, Ryuichi OHORI, Toshiya SHIMIZU, Takeshi SHIMOYAMA, Jumpei YAMAGUCHI
  • Patent number: 9673430
    Abstract: A power supply device comprises plural battery cells having electrode portions, and bus bars connecting the electrode portions of the plural battery cells each other. The bus bar comprises a thin portion thinner than the other portion formed in at least one part of the end edge of the bus bar, and are welded to the electrode portion of the battery cell through the thin portion. The electrode portion comprises a pedestal portion, and an electrode terminal projecting from the pedestal portion, and the thin portion is disposed at the side surface of the electrode terminal. By this, at the time of welding the bus bar the thin portion is directly welded to the electrode portion, and without using other parts of the welding ring or the like the welding process is streamlined.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: June 6, 2017
    Assignee: SANYO ELECTRIC CO., LTD.
    Inventors: Takashi Seto, Toshiya Shimizu, Yoshiyuki Furukoji, Nobukazu Yamanishi, Yasuhiro Asai
  • Patent number: 9520585
    Abstract: An assembled battery comprises: multiple cells 30 each having external terminals including a negative electrode terminal 50 and a positive electrode terminal; a bus bar 40 which connects the external terminal of one of two adjacent cells 30 and that of the other thereof; an electrically-conductive connecting member 70 which connects the external terminal and the bus bar 40 by welding to the external terminal and the bus bar 40; a welding portion 80 welded to the bus bar 40 and the connecting member 70; and a welding portion 82 welded to the external terminal and the connecting member 70. The connecting member 70 comprises an intervening portion 70b connected to the welding portion 80, and a main body portion 70a extending from the intervening portion 70b to the welding portion 82. The intervening portion 70b has a thickness that is smaller than that of the main body portion 70a.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: December 13, 2016
    Assignee: SANYO ELECTRIC CO., LTD.
    Inventors: Toshiya Shimizu, Kiyoshi Shibata, Yasuhiro Kohara, Yasuhiro Asai, Takashi Seto, Daiki Uchiyama
  • Publication number: 20150243947
    Abstract: A power supply device comprises plural battery cells having electrode portions, and bus bars connecting the electrode portions of the plural battery cells each other. The bus bar comprises a thin portion thinner than the other portion formed in at least one part of the end edge of the bus bar, and are welded to the electrode portion of the battery cell through the thin portion. The electrode portion comprises a pedestal portion, and an electrode terminal projecting from the pedestal portion, and the thin portion is disposed at the side surface of the electrode terminal. By this, at the time of welding the bus bar the thin portion is directly welded to the electrode portion, and without using other parts of the welding ring or the like the welding process is streamlined.
    Type: Application
    Filed: October 1, 2013
    Publication date: August 27, 2015
    Inventors: Takashi Seto, Toshiya Shimizu, Yoshiyuki Furukoji, Nobukazu Yamanishi, Yasuhiro Asai
  • Publication number: 20140057157
    Abstract: An assembled battery comprises: multiple cells 30 each having external terminals including a negative electrode terminal 50 and a positive electrode terminal; a bus bar 40 which connects the external terminal of one of two adjacent cells 30 and that of the other thereof; an electrically-conductive connecting member 70 which connects the external terminal and the bus bar 40 by welding to the external terminal and the bus bar 40; a welding portion 80 welded to the bus bar 40 and the connecting member 70; and a welding portion 82 welded to the external terminal and the connecting member 70. The connecting member 70 comprises an intervening portion 70b connected to the welding portion 80, and a main body portion 70a extending from the intervening portion 70b to the welding portion 82. The intervening portion 70b has a thickness that is smaller than that of the main body portion 70a.
    Type: Application
    Filed: February 27, 2012
    Publication date: February 27, 2014
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Toshiya Shimizu, Kiyoshi Shibata, Yasuhiro Kohara, Yasuhiro Asai, Takashi Seto, Daiki Uchiyama
  • Patent number: 8344522
    Abstract: The invention provides a solder structure which is least likely to develop Sn whiskers and a method for forming such a solder structure. The solder structure includes an Sn alloy capable of a solid-liquid coexistent state and an Au (or Au alloy) coating covering at least part of the surface of the Sn alloy. The Au covering is a film that covers and coats at least part of the surface of the Sn alloy. As a preferable mode, the Au coating forms a netlike structure on the surface of the Sn alloy. The thickness of the Au coating is, for instance, 1 to 5 ?m.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: January 1, 2013
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideki Mizuhara, Hajime Kobayashi, Toshiya Shimizu
  • Patent number: 8258409
    Abstract: Provided are a circuit board with enhanced moisture resist and the method of manufacturing the circuit board, and a circuit device and a method of manufacturing the circuit device. A circuit board of the present invention includes: a substrate; wirings formed on the main surface of the substrate; a cover layer covering the wirings excluding the regions to be connectors; back electrodes formed on the bottom surface of the substrate; and through-hole electrodes formed so as to penetrate the substrate, and thereby connecting the wirings and the back electrodes. On surfaces of each of the wirings in this circuit board, convex portions on the periphery of the substrate are set larger in width than convex portions in a center portion of the substrate. With this configuration, adhesion reliability between the wirings and the cover layer under a thermal cycle load can be enhanced.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: September 4, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuhiro Kohara, Kiyoshi Shibata, Masayuki Nagamatsu, Ryosuke Usui, Toshiya Shimizu
  • Publication number: 20120211269
    Abstract: A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 23, 2012
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Kouichi SAITOU, Toshiya SHIMIZU
  • Publication number: 20110127669
    Abstract: The invention provides a solder structure which is least likely to develop Sn whiskers and a method for forming such a solder structure. The solder structure includes an Sn alloy capable of a solid-liquid coexistent state and an Au (or Au alloy) coating covering at least part of the surface of the Sn alloy. The Au covering is a film that covers and coats at least part of the surface of the Sn alloy. As a preferable mode, the Au coating forms a netlike structure on the surface of the Sn alloy. The thickness of the Au coating is, for instance, 1 to 5 ?m.
    Type: Application
    Filed: March 18, 2009
    Publication date: June 2, 2011
    Inventors: Hideki Mizuhara, Hajime Kobayashi, Toshiya Shimizu