Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: A semiconductor integrated circuit, comprises a first reference voltage line; a second reference voltage line; a plurality of single logic circuits each including a plurality of transistors; a first switch having a first transistor provided between said first reference voltage line and said logic circuits, said first transistor having a higher threshold voltage than that of transistors in the logic circuits; and a second switch having a second transistor provided a between said second transistor having a higher threshold voltage than that of transistors in the logic circuits, said first and second switches being turned on when at least one of said single logic circuits is in operation, while said first and second switches being turned off when all of said single logic circuits are in standby state.

Abstract: There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced. In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.

Abstract: A computer device includes a computer processing circuit and a software development circuit. The computer processing circuit includes a first computing component and a first command control component, the first computing component performs calculations in accordance with a first control signal and the first control signal is generated by the first command control component based on a first program. The software development and support circuit includes a second computing component and a second command control component, the second computing component calculates in accordance with a second control signal and the second command control component generates the second control signal based on a second program. The software development and support circuit receives information of computing status of the computer processing circuit as numerical data, and the second computing component processes the numerical data responsive to the said second control signal.

Abstract: A digital signal processor (DSP) of high speed and high precision is disclosed. The DSP (i.e., digital arithmetic integrated circuit) comprises: an arithmetic data storing memory (11) for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit word length and the second arithmetic data string being composed of (m×n)-bits of a unit word length; two arithmetic operand storing registers (12) for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle (13); and an arithmetic result storing register (15) for storing the arithmetic results outputted by said arithmetic logical unit.

Abstract: A semiconductor integrated circuit, comprises a first reference voltage line; a second reference voltage line;

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: An automatic circuit generation methods and apparatus (1) provide a desired circuit performance by reducing a leakage current during both a standby state and an active state, where cells having only High-Vth and Mt cells having both High-Vth transistors and Low-Vth translators are optimally mixed in a logical circuit. It is thereby possible to suppress efficiently the leakage current, in a design stage, generated according to miniaturization of LSI layout design and also lowering a supply voltage to the LSI.

Abstract: In a digital signal processor for pipeline processing divided into at least three steps, i.e., instruction fetch cycle, instruction decode cycle and instruction execution cycle, a value of a register (A) is put on a data bus assuming the condition is consistent when a condition execution instruction is decoded in an instruction decoder (14). Then, in the instruction execution cycle of the condition execution instruction, a register (B) introduced the value on the data bus when upon consistency of the condition. As a result, even before a condition flag (Z) changes as a result of execution of the instruction for generating the condition in the instruction execution cycle, the condition execution instruction can be decoded. Thus, the processor may omit an instruction other than “condition generation instruction or condition execution instruction” which was conventionally required.

Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

Abstract: There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced.

Abstract: An automatic circuit generation methods and apparatus (1) provide a desired circuit performance by reducing a leakage current during both a standby state and an active state, where cells having only High-Vth and Mt cells having both High-Vth transistors and Low-Vth translators are optimally mixed in a logical circuit. It is thereby possible to suppress efficiently the leakage current, in a design stage, generated according to miniaturization of LSI layout design and also lowering a supply voltage to the LSI.

Abstract: A digital signal processor (DSP) of high speed and high precision is disclosed. The DSP (i.e., digital arithmetic integrated circuit) comprises: an arithmetic data storing memory (11) for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit word length and the second arithmetic data string being composed of (m×n)-bits of a unit word length; two arithmetic operand storing registers (12) for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle (13); and an arithmetic result storing register (15) for storing the arithmetic results outputted by said arithmetic logical unit.

Abstract: A digital signal processor (DSP) of high speed and high precision is disclosed. The DSP (i.e., digital arithmetic integrated circuit) comprises: an arithmetic data storing memory (11) for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit wiord length and the second arithmetic data string being composed of (m.times.n)-bits of a unit word length; two arithmetic operand storing registers (12) for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle (13); and an arithmetic result storing register (15) for storing the arithmetic results outputted by said arithmetic logical unit.

Abstract: A digital computation integrated circuit has instruction memory for storing an instruction data, a store address designating part for designating a storing address of the instruction data in the instruction memory and for outputting the instruction data; an instruction decoder for receiving the instruction data outputted from the instruction memory and for converting the instruction data into a control signal to be outputted; an address determining part for determining an address necessary to reproduce history of a program when decoding result by the instruction decoder is found that the instruction data represent nonsequential progress of a program; and an address memory for storing the address necessary to reproduce history of a program in a storing address thereof designated by the storing address determining part.