Patents by Inventor Toshiyuki Hayakawa

Toshiyuki Hayakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020058746
    Abstract: The invention provides a flame-retardant rubber composition which may form a vulcanizate of an elastomer whose deterioration of mechanical strength is little to enjoy excellent mechanical properties, even when a nonhalogenated flame retardant is contained in a high proportion in the composition, and a flame-retardant elastomer obtained therefrom.
    Type: Application
    Filed: September 10, 2001
    Publication date: May 16, 2002
    Applicant: JSR Corporation
    Inventors: Shoei Tsuji, Junji Ayukawa, Toshiyuki Hayakawa, Minoru Tanaka, Fumio Tsutsumi
  • Patent number: 5976934
    Abstract: In a method of manufacturing a nonvolatile semiconductor memory device, a first polysilicon conductive layer, which is formed in a peripheral circuit region on a semiconductor substrate with a third gate insulating film interposed therebetween, is patterned into the shape of a gate electrode. A gate bird's beak is formed below the gate electrode in the peripheral circuit region by means of a heat treatment in an oxidizing atmosphere. Subsequently, in a memory cell array region, the first polysilicon conductive layer and a second polysilicon conductive layer laminated thereabove are processed to obtain a stacked gate structure.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: November 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Hayakawa
  • Patent number: 5766996
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming memory cell sections in a nonvolatile semiconductor memory device which has the memory cell sections and peripheral circuit transistor sections formed on a semiconductor substrate, coating a stacked region of the memory cell sections and a top surface of the peripheral circuit transistor sections with an oxidation-resistant layer, and forming an oxide layer over the surface of the semiconductor substrate by thermal oxidation. The peripheral circuit transistor gate oxide layer is suitably oxidized to have sufficient dielectric strength while preventing the interlayer insulating layer between the control gate edge and the floating gate edge of a memory cell from being oxidized more than necessary.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: June 16, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Hayakawa, Seiichi Aritome
  • Patent number: 5754558
    Abstract: According to a method for screening a nonvolatile semiconductor memory device, data is written to all memory cells. The data is slightly erased such that the memory cells have a positive distribution of threshold voltages. The threshold voltages of the memory cells are measured, and the number of memory cells whose threshold voltages are lower than a reference threshold voltage, is counted. When the counted number is not larger than the number of spare cells provided in a redundant circuit, the memory cells whose threshold voltages are lower than the reference threshold voltage are replaced with the spare cells. When the counted number is larger than the number of spare cells, the nonvolatile semiconductor memory device is determined as a defective one.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: May 19, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Hayakawa, Seiji Yamada
  • Patent number: 5479088
    Abstract: The DC-DC converter is disclosed, which has an output terminal connected to an external load, and produces a desired output voltage at the output terminal. An output capacitor in the converter has a first electrode connected to the output terminal and a second electrode. The charge/discharge regulator controls electrical connection between a DC power supply and the output capacitor to permit the capacitor to be charged or discharged. The DC-DC converter includes a first detecting circuit for detecting a change in the output voltage at the output terminal, and a second detecting circuit for detecting a variable load current flowing into the converter from the load via the output terminal.
    Type: Grant
    Filed: July 22, 1994
    Date of Patent: December 26, 1995
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Toshiyuki Hayakawa, Hidenobu Ito, Shinichi Nakagawa
  • Patent number: 5464998
    Abstract: A non-volatile semiconductor memory device includes NAND type memory cells arranged in a matrix pattern over a semiconductor substrate and channel stopper layers, provided on the substrate, for separating adjacent NAND type memory cells. Each NAND type memory cell includes memory cell transistors having drains and sources mutually connected in series, a source side select transistor connected to a source of one end transistor of the memory cell transistors, and a drain side select transistor connected to a drain of the other end transistor of the memory cell transistors. Each channel stopper layer has a first layer portion for separating the source side select transistors and a second layer portion for separating the memory cell transistors. Impurity concentration of the first layer portion is lower than that of the second layer portion.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: November 7, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Hayakawa, Ryouhei Kirisawa