Patents by Inventor Toyohiro Aoki
Toyohiro Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12183708Abstract: A semiconductor structure includes a wafer having a wafer outer surface; a semiconductor chip; and a plurality of copper pillars on the semiconductor chip. The pillars have curved end portions and pillar outside surfaces. Also included are a plurality of copper pads on the wafer. The pads have end portions aligned with the curved end portions of the plurality of copper pillars on the semiconductor chip, and the curved end portions of the plurality of copper pillars and the end portions of the plurality of copper pads define a plurality of bonding material receiving regions. The pads have pad outside surfaces. A copper bonding layer is on the pillar outside surfaces, the pad outside surfaces, the bonding material receiving regions, and portions of the outer surface of the wafer. The portions have an annular shape about the copper pads when viewed in plan.Type: GrantFiled: January 31, 2022Date of Patent: December 31, 2024Assignee: International Business Machines CorporationInventors: Koki Nakamura, Toyohiro Aoki, Takashi Hisada
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Patent number: 12166008Abstract: An apparatus for injecting solder material in via holes located in a top surface of a wafer is provided. The apparatus includes an injection head having a contact surface for contacting the top surface of the wafer, and at least one aperture for injecting the solder material though the injection head into the via holes. The apparatus further includes an evacuating device connected to the injection head for evacuating gas from the via holes. The injection head has a chamfer part on an edge of a contact surface contacting the top surface of the wafer.Type: GrantFiled: November 18, 2021Date of Patent: December 10, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sayuri Hada, Toyohiro Aoki, Takashi Hisada, Shintaro Yamamichi
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Patent number: 12142603Abstract: Interconnecting a first chip and a second chip includes mounting the first and second chips to a chip handler having an opening and at least one support surface. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The first surface of the first chip and the first surface of the second chip mounted to the chip handler are supported by the at least one support surface of the chip handler. The first and second chips are placed on a chip support member with the chip handler from the second surfaces. A bridge member is inserted by a bridge handler through the opening of the chip handler to place the bridge member onto the first sets of terminals of the first and second chips that are exposed from the opening.Type: GrantFiled: May 26, 2023Date of Patent: November 12, 2024Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Takahito Watanabe, Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori
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Patent number: 12094825Abstract: A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.Type: GrantFiled: June 29, 2023Date of Patent: September 17, 2024Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Toyohiro Aoki, Takashi Hisada
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Publication number: 20240282735Abstract: Methods, systems, and structures relating to flip-chip bonding are described. A processor can determine a plurality of target solder volumes to be deposited on a plurality of pads on a surface of a substrate. The plurality of target solder volumes can be variable among the plurality of pads. The processor can determine different thicknesses of different portions of a layer of resist to be deposited across the surface of the substrate. The different thicknesses can define a plurality of solder resist openings having sizes that comply with the plurality of target solder volumes.Type: ApplicationFiled: February 21, 2023Publication date: August 22, 2024Inventors: Toyohiro Aoki, Katsuyuki Sakuma, Hiroyuki Mori, Koki Nakamura, Takashi Hisada
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Patent number: 11969828Abstract: An injection apparatus for injection material is disclosed. The injection apparatus includes a tank for storing material. The injection apparatus further includes a head body that has a surface for contacting a substrate and an opening part opened at the surface for discharging the material in fluid-communication with the tank. The injection apparatus further includes a member connected to the opening part, in which the member allows gas to flow into and flow out from the opening part.Type: GrantFiled: April 6, 2023Date of Patent: April 30, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toyohiro Aoki, Eiji Nakamura, Takashi Hisada
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Publication number: 20240112965Abstract: A semiconductor device includes a substrate, which further includes a cavity and a trench extended from the cavity. The semiconductor includes a first chip and a second chip on the substrate, a bridge chip interconnecting between the first and second chips and residing in the cavity, and underfill material filling the cavity and the trench, and surrounding the bridge chip.Type: ApplicationFiled: October 3, 2022Publication date: April 4, 2024Inventors: Chinami Marushima, Toyohiro Aoki, Takashi Hisada, Marc A. Bergendahl
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Publication number: 20240006371Abstract: An interconnect system may connect a first semiconductor device with second semiconductor device. The interconnect system includes patterned mask, conductive pads, solder bumps, and an adhesion layer. The patterned mask may be retained after it is utilized to fabricate the conductive pads and the solder bumps. The patterned mask may be thinned, and the adhesion layer may be formed upon the thinned patterned mask and upon the solder bumps. The adhesion layer and the solder bumps may be partially removed or planarized and the top surface of the adhesion layer that remains between the solder bumps may be coplanar with the top surface of the solder bumps.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Keiji Matsumoto, Toyohiro Aoki, Takahito Watanabe, RISA MIYAZAWA, Takashi Hisada
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Patent number: 11848272Abstract: A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.Type: GrantFiled: August 16, 2021Date of Patent: December 19, 2023Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Toyohiro Aoki, Takashi Hisada
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Publication number: 20230343713Abstract: A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Akihiro Horibe, Toyohiro Aoki, Takashi Hisada
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Publication number: 20230317652Abstract: A semiconductor device includes two integrated circuit (IC) chips. The first IC chip includes substrate, a spacer connected to the substrate and including holes, wherein at least one of the holes has a first shape, and solder bumps positioned in the holes, respectively. The second IC chip includes a substrate, electrode pads extending from the substrate and connected to the solder bumps, respectively. At least one of the electrode pads that corresponds to the at least one of the solder bumps has a second shape, and the first shape and the second shape are non-coextensive such that there is at least one gap between the first shape and the second shape when projected on each other.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Toyohiro Aoki, KOKI NAKAMURA, Takashi Hisada
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Publication number: 20230307307Abstract: An interconnected semiconductor subassembly structure includes an interconnect structure; a first semiconductor die bonded to a first portion of a top surface of the interconnect structure; a second semiconductor die bonded to a second portion of the top surface of the interconnect structure; and a resin layer located within at least a first portion of a gap between the first semiconductor die and the second semiconductor die, wherein at least one of a top surface and a bottom surface of the resin layer located within the at least first portion of the gap has a concave meniscus shape.Type: ApplicationFiled: September 11, 2022Publication date: September 28, 2023Inventors: Akihiro Horibe, Toyohiro Aoki, CHINAMI MARUSHIMA, Takahito Watanabe, Takashi Hisada
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Publication number: 20230299067Abstract: Interconnecting a first chip and a second chip includes mounting the first and second chips to a chip handler having an opening and at least one support surface. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The first surface of the first chip and the first surface of the second chip mounted to the chip handler are supported by the at least one support surface of the chip handler. The first and second chips are placed on a chip support member with the chip handler from the second surfaces. A bridge member is inserted by a bridge handler through the opening of the chip handler to place the bridge member onto the first sets of terminals of the first and second chips that are exposed from the opening.Type: ApplicationFiled: May 26, 2023Publication date: September 21, 2023Inventors: Akihiro Horibe, Takahito Watanabe, Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori
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Patent number: 11735575Abstract: Interconnecting a first chip and a second chip by a bridge member includes a chip handler for handling the first chip and the second chip. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The chip handler has an opening and at least one support surface for supporting the first surfaces of the first chip and the second chip when the first chip and the second chip are mounted to the chip handler. A chip support member supports the first chip and the second chip from the second surfaces, and a bridge handler is provided for inserting the bridge member through the opening of the chip handler and for placing the bridge member onto the first sets of terminals of the first chip and the second chip.Type: GrantFiled: May 27, 2021Date of Patent: August 22, 2023Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Takahito Watanabe, Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori
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Publication number: 20230241700Abstract: An injection apparatus for injection material is disclosed. The injection apparatus includes a tank for storing material. The injection apparatus further includes a head body that has a surface for contacting a substrate and an opening part opened at the surface for discharging the material in fluid-communication with the tank. The injection apparatus further includes a member connected to the opening part, in which the member allows gas to flow into and flow out from the opening part.Type: ApplicationFiled: April 6, 2023Publication date: August 3, 2023Inventors: Toyohiro Aoki, Eiji Nakamura, Takashi Hisada
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Publication number: 20230245997Abstract: A semiconductor structure includes a wafer having a wafer outer surface; a semiconductor chip; and a plurality of copper pillars on the semiconductor chip. The pillars have curved end portions and pillar outside surfaces. Also included are a plurality of copper pads on the wafer. The pads have end portions aligned with the curved end portions of the plurality of copper pillars on the semiconductor chip, and the curved end portions of the plurality of copper pillars and the end portions of the plurality of copper pads define a plurality of bonding material receiving regions. The pads have pad outside surfaces. A copper bonding layer is on the pillar outside surfaces, the pad outside surfaces, the bonding material receiving regions, and portions of the outer surface of the wafer. The portions have an annular shape about the copper pads when viewed in plan.Type: ApplicationFiled: January 31, 2022Publication date: August 3, 2023Inventors: KOKI NAKAMURA, Toyohiro Aoki, Takashi Hisada
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Patent number: 11684988Abstract: An injection apparatus for injection material is disclosed. The injection apparatus includes a tank for storing material. The injection apparatus further includes a head body that has a surface for contacting a substrate and an opening part opened at the surface for discharging the material in fluid-communication with the tank. The injection apparatus further includes a member connected to the opening part, in which the member allows gas to flow into and flow out from the opening part.Type: GrantFiled: March 9, 2022Date of Patent: June 27, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toyohiro Aoki, Eiji Nakamura, Takashi Hisada
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Publication number: 20230178445Abstract: An electronic device is formed by dispensing an underfill material around a perimeter of an integrated circuit (IC) chip bonded to a supporting substrate. A void in present in the underfill material that is present between the IC chip and the supporting substrate. An opening is present through at least one of the IC chip and the supporting substrate into communication with the void. A vacuum may be applied to the void through the opening that is present through the IC chip to reduce a size of the void to a first volume. The opening that is present through the IC chip is sealed with a sealing plate. The underfill material is cured after the sealing of the opening to reduce of the void to at least a second volume that is less than the first volume.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Inventors: Toyohiro Aoki, CHINAMI MARUSHIMA, RISA MIYAZAWA, Akihiro Horibe, Takashi Hisada
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Publication number: 20230154887Abstract: An apparatus for injecting solder material in via holes located in a top surface of a wafer is provided. The apparatus includes an injection head having a contact surface for contacting the top surface of the wafer, and at least one aperture for injecting the solder material though the injection head into the via holes. The apparatus further includes an evacuating device connected to the injection head for evacuating gas from the via holes. The injection head has a chamfer part on an edge of a contact surface contacting the top surface of the wafer.Type: ApplicationFiled: November 18, 2021Publication date: May 18, 2023Inventors: Sayuri Hada, Toyohiro Aoki, Takashi Hisada, Shintaro Yamamichi
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Publication number: 20230051337Abstract: A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.Type: ApplicationFiled: August 16, 2021Publication date: February 16, 2023Inventors: Akihiro Horibe, Toyohiro Aoki, Takashi Hisada