Patents by Inventor Toyota Morimoto

Toyota Morimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR MEMORY SYSTEM
    Publication number: 20230307433
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: May 31, 2023
    Publication date: September 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
  • Semiconductor memory system
    Patent number: 11705444
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: July 18, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • SEMICONDUCTOR MEMORY SYSTEM
    Publication number: 20210296300
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: June 9, 2021
    Publication date: September 23, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
  • Semiconductor memory system
    Patent number: 11063031
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 13, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • SEMICONDUCTOR MEMORY SYSTEM
    Publication number: 20200194414
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
  • Semiconductor memory system
    Patent number: 10607979
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 31, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • SEMICONDUCTOR MEMORY SYSTEM
    Publication number: 20190326275
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
  • Semiconductor memory system
    Patent number: 10388640
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • SEMICONDUCTOR MEMORY SYSTEM
    Publication number: 20180076186
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: November 24, 2017
    Publication date: March 15, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Hayato MASUBUCHI, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Semiconductor memory system
    Patent number: 9859264
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Semiconductor memory system
    Patent number: 9754632
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • SEMICONDUCTOR MEMORY SYSTEM
    Publication number: 20170092635
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: December 14, 2016
    Publication date: March 30, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
  • SEMICONDUCTOR MEMORY SYSTEM
    Publication number: 20160372159
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: September 1, 2016
    Publication date: December 22, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hayato MASUBUCHI, Naoki KIMURA, Manabu MATSUMOTO, Toyota MORIMOTO
  • Semiconductor memory system
    Patent number: 9437533
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: September 6, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Semiconductor memory system
    Patent number: 9312215
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: April 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • SEMICONDUCTOR MEMORY SYSTEM
    Publication number: 20150021783
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: October 10, 2014
    Publication date: January 22, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hayato MASUBUCHI, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • SEMICONDUCTOR MEMORY SYSTEM
    Publication number: 20140319675
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: July 7, 2014
    Publication date: October 30, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hayato MASUBUCHI, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Semiconductor memory system
    Patent number: 8873265
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • Semiconductor memory system
    Patent number: 8804393
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: August 12, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hayato Masubuchi, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto
  • SEMICONDUCTOR MEMORY SYSTEM
    Publication number: 20120235141
    Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 20, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hayato MASUBUCHI, Naoki Kimura, Manabu Matsumoto, Toyota Morimoto