Patents by Inventor Travis Eiles
Travis Eiles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10163601Abstract: A probe assembly for analyzing a test device that includes a housing with an electron source disposed therein for emitting primary electrons. A photon source is positioned to emit photons that strike the electron source such that when the photons strike the electron source, the electron source emits the primary electrons. Detection circuitry is provided that is configured to detect secondary electrons emitted from a test device of a test assembly and to form an excitation waveform.Type: GrantFiled: December 28, 2017Date of Patent: December 25, 2018Assignee: Intel CorporationInventors: Amir Raveh, Travis Eiles, Evgeny Gregory Nisenboim, Patrick Pardy
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Patent number: 7660054Abstract: Embodiments allow for uniform die cooling or heating with a solid immersion lens equipped microscope over a larger temperature range than is currently attainable using liquid coolant. The SIL tip is insulated from the rest of the objective body to realize a controllable temperature. This thermal control may be done by convection or Joule heating. If the tip is to be cooled, cold gas may be injected through channels around the tip and fins. If the tip is to be heated, hot gas may be injected around the tip and fins 208 or an electrical heater may be thermal anchored to the tip and a current passed through it to deliver power.Type: GrantFiled: June 29, 2007Date of Patent: February 9, 2010Assignee: Intel CorporationInventors: Cameron Wagner, David Shykind, Travis Eiles
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Publication number: 20090002855Abstract: Embodiments allow for uniform die cooling or heating with a solid immersion lens equipped microscope over a larger temperature range than is currently attainable using liquid coolant. The SIL tip is insulated from the rest of the objective body to realize a controllable temperature. This thermal control may be done by convection or Joule heating. If the tip is to be cooled, cold gas may be injected through channels around the tip and fins. If the tip is to be heated, hot gas may be injected around the tip and fins 208 or an electrical heater may be thermal anchored to the tip and a current passed through it to deliver power.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Inventors: Cameron Wagner, David Shykind, Travis Eiles
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Patent number: 7410858Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.Type: GrantFiled: May 19, 2006Date of Patent: August 12, 2008Assignee: Intel CorporationInventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
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Patent number: 7411269Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.Type: GrantFiled: March 28, 2005Date of Patent: August 12, 2008Assignee: Intel CorporationInventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
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Publication number: 20070013023Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.Type: ApplicationFiled: September 22, 2006Publication date: January 18, 2007Inventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
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Publication number: 20060249859Abstract: Using imaging techniques to determine if stacked wafers are in proper alignment. An infrared radiation source and an infrared camera are positioned on opposing sides of a stacked wafer. The infrared radiation source emits infrared radiation that penetrates and passes through the stacked wafer. The infrared radiation is then captured by the infrared camera. Fiducial marks that were previously patterned on each wafer of the stack are exposed in an image produced by the captured infrared radiation. The degree of alignment of the wafers can be measured using the fiducial marks exposed in the image.Type: ApplicationFiled: May 5, 2005Publication date: November 9, 2006Inventors: Travis Eiles, Shriram Ramanathan
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Publication number: 20060220147Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.Type: ApplicationFiled: May 19, 2006Publication date: October 5, 2006Inventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
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Publication number: 20050179109Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.Type: ApplicationFiled: March 28, 2005Publication date: August 18, 2005Inventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
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Patent number: 6882170Abstract: Integrated circuit and integrated circuit device diagnostic methods and apparatus in accordance with the present invention are provided. The IC is operated to produce an output marginally above a pass-fail threshold for a particular performance criteria. The IC is made to fail that criteria by inducing an electrical stress in an IC device that is of marginal design for that particular criteria. The electrical stress acts to minutely degrade the performance of the IC device driving the IC below the pass-fail threshold. When each IC device is stressed in accordance with the embodiments of the present invention, marginal IC devices are identified to enable the design to be modified. The induced electrical stress is non-destructive to the IC device and IC, which permits a repeatable diagnostic process, as well as allows for the diagnostic testing of other IC devices in the same microcircuit.Type: GrantFiled: December 5, 2002Date of Patent: April 19, 2005Assignee: Intel CorporationInventors: Travis Eiles, Jeremy A. Rowlette
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Patent number: 6876053Abstract: An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.Type: GrantFiled: August 13, 1999Date of Patent: April 5, 2005Assignee: Intel CorporationInventors: Qing Ma, Jin Lee, Harry Fujimoto, Changhong Dai, Shiuh-Wuu Lee, Travis Eiles, Krishna Seshan
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Publication number: 20040108868Abstract: Integrated circuit and integrated circuit device diagnostic methods and apparatus in accordance with the present invention are provided. The IC is operated to produce an output marginally above a pass-fail threshold for a particular performance criteria. The IC is made to fail that criteria by inducing an electrical stress in an IC device that is of marginal design for that particular criteria. The electrical stress acts to minutely degrade the performance of the IC device driving the IC below the pass-fail threshold. When each IC device is stressed in accordance with the embodiments of the present invention, marginal IC devices are identified to enable the design to be modified. The induced electrical stress is non-destructive to the IC device and IC, which permits a repeatable diagnostic process, as well as allows for the diagnostic testing of other IC devices in the same microcircuit.Type: ApplicationFiled: December 5, 2002Publication date: June 10, 2004Inventors: Travis Eiles, Jeremy A. Rowlette