Isolation structure configurations for modifying stresses in semiconductor devices
An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.
1. Field of the Invention
The present invention relates to apparatus and methods for modifying stresses in semiconductor devices. In particular, the present invention relates to modifying isolation structure configurations, such as trench depth and isolation materials used, to either induce or reduce tensile and/or compressive stresses on an active area of MOS semiconductor devices.
2. State of the Art
Semiconductor integrated circuits are formed by chemically and physically forming circuit components in and on a semiconductor substrate. These circuit components are generally conductive (e.g., for conductor and resistor fabrication) and may be of different conductivity types (e.g., for transistor and diode fabrication). Thus, when forming such circuit components, it is essential that they are electrically isolated from one another, wherein electrical communication between the isolated circuit components is achieved through discrete electrical traces.
Various techniques have been developed for electrically isolating integrated circuit components formed in the semiconductor substrate. One such technique is known as trench isolation. The trench isolation technique involves forming a channel or trench in the semiconductor substrate, usually by etching techniques well known in the art. The trench is formed to surround the circuit components to be isolated and filled with a dielectric material, thereby electrically isolating the circuit components.
A gate structure 208 spans a region of the semiconductor substrate 206 between the source region 202 and the drain region 204. An exemplary gate structure 208 comprises a conductive material 212 electrically isolated with dielectric spacers 214 and 214′ adjacent the source region 202 and the drain region 204, a lower dielectric layer 216, and a cap layer 218.
The source region 202 and the drain region 204 are isolated with an isolation structure 222 (i.e., a dielectric-filled trench) extending into the semiconductor substrate 206, preferably beyond the depth of the source region 202 and the drain region 204, as shown in
It has been reported in literature that stresses on an active area can significantly effect the performance of MOS devices. Hamada in “A New Aspect of Mechanical Stress Effects in Scaled MOS Device”, IEEE Transactions on Electron Devices, vol. 38 (1991), pp. 895-900 illustrated that stresses of the order of 100 MPa can affect performance by a few percent. In the reported experiments, well-controlled uniaxial stresses were applied on MOS devices by using a 4-point bending technique. The stresses were applied both parallel and perpendicular to the channel current direction and for both NMOS and pMOS devices. The results showed that for nMOS devices, tensile stress in both directions improves performance, while compressive stress degrades performance. These effects have been found to be more significant for long channel nMOS devices. For pMOS devices, tensile stress perpendicular to the channel current direction improves performance, but tensile stress parallel to the channel current direction degrades performance, and vice versa for compressive stress.
Such degradation in performance is particularly a problem for MOS devices in flip-chip packaging configurations.
As previously discussed, these biaxial stresses will degrade nMOS device performance. However, these biaxial stresses will have less of an effect on the performance of a pMOS device due to the cancellation effects of the two perpendicular stress components (i.e., the decrease in performance due to compressive stress perpendicular to the channel current direction is offset by the increase in performance due to the compressive stress parallel to the channel current direction).
Therefore, it would be advantageous to develop a technique to effectively induce or reduce tensile and/or compressive stresses on the active area of a MOS device to improve the operating performance thereof, while utilizing commercially-available, widely-practiced semiconductor device fabrication techniques.
SUMMARY OF THE INVENTIONThe present invention relates to apparatus and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device. In specific, the present invention relates to a semiconductor device having an active area formed in a semiconductor substrate and an isolation structure comprising at least one dielectric material disposed within a trench which extends into said semiconductor substrate, wherein the isolation structure substantially surrounds the active area, and wherein at least a portion of the isolation structure is adapted to modify stresses incurred on the active area.
The modification of isolation structure configurations is an effective technique of controlling stresses on a semiconductor device active because the isolation structure is on the same relative plane as the active area and, of course, any device structures formed therein. This shared plane allows for a direct transfer or abatement of stresses incurred on the active area due to packaging or other external stress sources.
BRIEF DESCRIPTION OF THE DRAWINGSWhile the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings to which:
Although
It is recognized that it would be advantageous to modify the stresses acting upon the active area of a MOS device in order to improve performance. Such stress modification might be achieved at the packaging level by applying stresses to the semiconductor die. However, semiconductor dice are usually brittle and break easily under stress. Additionally, it is very difficult to apply a uniform stress across an entire semiconductor die. Thus, an attempt to apply a uniform stress across the semiconductor die would likely result in a non-uniform stress which would, in turn, result in undesirable performance variations in the MOS devices across the semiconductor die.
The source region 102 and the drain region 104 are isolated with an isolation structure 122, which extends into the semiconductor substrate 106. The isolation structure 122 surrounds the source region 102 and the drain region 104, as shown in
It is, of course, understood that the use of low-modulus, dielectric material can also improve pMOS device performance in back-bonded packaging configurations.
Of course, these biaxial tensile stresses enhance the performance of NMOS devices, but have little effect on the performance of a pMOS device, due to the cancellation effects of the two perpendicular stress components. However, the low-modulus, dielectric material 126 can be used to improve the performance a pMOS device. As shown in
A further embodiment of the present invention involves increasing isolation structure depth to reduce compressive stresses.
As illustrated in
When the pMOS device 190 is subjected to biaxial tensile stresses (e.g., back-bonded packaging configurations), the isolation structure depth is increased for the isolation structure depth is increased only in portions 192 of the isolation structure 122 which are perpendicular to the channel current direction in order to eliminate or lessen the detrimental tensile stresses parallel to the channel current direction, as shown in
It is also understood, that the introduction of various low-modulus and high-modulus dielectric material, and compressive stress-inducing and tensile stress-inducing, dielectric materials may degrade the interface between the active area and the dielectric material and cause leakage problems. Thus, a thin conformal barrier layer 196, such as a conformal layer of silicon dioxide 196 may be deposited in the isolation structure 122 prior to depositing any of the various dielectric materials 198, as shown
Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
Claims
1-30. (canceled)
31. A structure comprising:
- a substrate;
- a first transistor disposed over a first region of the substrate, the first transistor including: a first source region and a first drain region disposed in a first portion of the substrate, a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of strain, and a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material; and
- a first trench structure disposed in a trench wherein the trench is proximate at least one side of one of the first source region and the first drain region, the first trench structure inducing only a portion of the first type of strain in the first channel region.
32. The structure of claim 31, further comprising:
- a strained layer disposed over the substrate,
- wherein at least a portion of the first channel region is disposed in the strained layer, and the strained layer comprises at least one of a group II, group III, group V, and group VI element.
33. The structure of claim 31, further comprising:
- a first strain-inducing element that induces strain in the first channel region; and
- a second strain-inducing element that induces strain in the first channel region,
- wherein the portion of the strain induced by the first trench structure is approximately zero and the first strain-inducing element is different from the second strain-inducing element.
34. The structure of claim 33 wherein the first strain-inducing element comprises a first cap layer disposed over a surface of the first transistor.
35. The structure of claim 33 wherein the first strain-inducing element comprises the first gate.
36. The structure of claim 33 wherein the first strain-inducing element comprises at least one of the first source region and the first drain region.
37. A method for forming a semiconductor structure, the method comprising:
- providing a substrate;
- forming a first transistor over a first region of the substrate by: defining a first source region and a first drain region in a first portion of the substrate, defining a first channel region between the first source region and the first drain region, the first channel region having a first type of strain, and forming a first gate above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material; and
- forming a first trench proximate at least one side of one of the first source region and the first drain region; and
- forming a first trench structure in the first trench, the first trench structure tailored to induce only a portion of the first type of strain in the first channel region.
38. The method of claim 37 wherein at least a portion of the strain in the first channel region is induced by the first gate.
39. The method of claim 37, further comprising:
- providing a first strain-inducing element; and
- providing a second strain-inducing element different from the first strain-inducing element,
- wherein the portion of the strain induced by the first trench structure is approximately zero.
40. The method of claim 39 wherein the first strain-inducing element comprises a first cap layer disposed over a surface of the first transistor.
41. The method of claim 39 wherein the first strain-inducing element comprises the first gate.
42. The method of claim 39 wherein the first strain-inducing element comprises at least one of the first source region and the first drain region.
43. The structure of claim 31, further comprising:
- a dielectric layer disposed beneath the first channel region.
44. The structure of claim 31 wherein at least one of the first source region and the first drain region comprises a metal-semiconductor alloy, and the strain in the first channel region is induced by the metal-semiconductor alloy.
45. The structure of claim 31 wherein the first transistor is disposed in a chip, the structure further comprising:
- a package housing the chip,
- wherein the package induces strain in the first channel region.
46. The structure of claim 33 wherein the first strain-inducing element comprises a metal-semiconductor alloy region disposed within at least one of the first source region and the first drain region.
47. The method of claim 37, further comprising:
- forming a metal-semiconductor alloy over at least one of the first source region and the first drain region, the metal-semiconductor alloy tailored to induce the first type of strain in the first channel region.
48. The method of claim 38 wherein forming the first gate comprises depositing an overlayer over the first gate and annealing the first gate.
49. The method of claim 38 wherein forming the first gate comprises forming a polycrystalline semiconductor layer over the substrate and reacting the polycrystalline semiconductor layer with a metal such that the first gate consists essentially of an alloy of the metal and the semiconductor layer.
50. The method of claim 37 wherein the first transistor is disposed in a chip, the method further comprising:
- attaching the chip to a package,
- wherein at least a portion of the strain in the first channel region is induced by the package.
51. The method of claim 39 wherein the first strain-inducing element comprises a metal-semiconductor alloy formed over at least one of the first source region and the first drain region.
52. A method for forming a semiconductor structure, the method comprising:
- providing a substrate comprising a strained layer having a first type of strain;
- forming a masking layer over the substrate such that the masking layer exerts a second type of strain on the strained layer;
- removing the masking layer over a first portion of the substrate; and
- etching a trench in the first portion of the substrate.
53. The method of claim 52 wherein the first type of strain and the second type of strain are different.
54. The method of claim 52 wherein the masking layer comprises silicon nitride.
55. The method of claim 52, further comprising forming a pad oxide layer over the substrate prior to forming the masking layer.
56. A structure comprising:
- a substrate;
- a first transistor disposed over a first region of the substrate, the first transistor including: a first source region and a first drain region disposed in a first portion of the substrate, a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of stress, and a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material; and
- a first isolation structure disposed in a trench wherein the trench is proximate at least one side of one of the first source region and the first drain region, the first isolation structure inducing only a portion of the first type of stress in the first channel region.
57. The structure of claim 56, further comprising:
- a stressed layer disposed over the substrate,
- wherein at least a portion of the first channel region is disposed in the stressed layer, and the stressed layer comprises at least one of a group II, group III, group V, and group VI element.
58. The structure of claim 56, further comprising:
- a first stress-inducing element that induces stress in the first channel region; and
- a second stress-inducing element that induces stress in the first channel region,
- wherein the portion of the stress induced by the first isolation structure is approximately zero and the first stress-inducing element is different from the second stress-inducing element.
59. The structure of claim 58 wherein the first stress-inducing element comprises a first cap layer disposed over a surface of the first transistor.
60. The structure of claim 58 wherein the first stress-inducing element comprises the first gate.
61. The structure of claim 58 wherein the first stress-inducing element comprises at least one of the first source region and the first drain region.
62. A method for forming a semiconductor structure, the method comprising:
- providing a substrate;
- forming a first transistor over a first region of the substrate by: defining a first source region and a first drain region in a first portion of the substrate, defining a first channel region between the first source region and the first drain region, the first channel region having a first type of stress, and forming a first gate above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material; and
- forming a first trench proximate at least one side of one of the first source region and the first drain region; and
- forming a first isolation structure in the first trench, the first isolation structure tailored to induce only a portion of the first type of stress in the first channel region.
63. The method of claim 62 wherein at least a portion of the stress in the first channel region is induced by the first gate.
64. The method of claim 62, further comprising:
- providing a first stress-inducing element; and
- providing a second stress-inducing element different from the first stress-inducing element,
- wherein the portion of the stress induced by the first isolation structure is approximately zero.
65. The method of claim 64 wherein the first stress-inducing element comprises a first cap layer disposed over a surface of the first transistor.
66. The method of claim 64 wherein the first stress-inducing element comprises the first gate.
67. The method of claim 64 wherein the first stress-inducing element comprises at least one of the first source region and the first drain region.
68. The structure of claim 56, further comprising:
- a dielectric layer disposed beneath the first channel region.
69. The structure of claim 56 wherein at least one of the first source region and the first drain region comprises a metal-semiconductor alloy, and the stress in the first channel region is induced by the metal-semiconductor alloy.
70. The structure of claim 56 wherein the first transistor is disposed in a chip, the structure further comprising:
- a package housing the chip,
- wherein the package induces stress in the first channel region.
71. The structure of claim 58 wherein the first stress-inducing element comprises a metal-semiconductor alloy region disposed within at least one of the first source region and the first drain region.
72. The method of claim 62, further comprising:
- forming a metal-semiconductor alloy over at least one of the first source region and the first drain region, the metal-semiconductor alloy tailored to induce the first type of stress in the first channel region.
73. The method of claim 63 wherein forming the first gate comprises depositing an overlayer over the first gate and annealing the first gate.
74. The method of claim 63 wherein forming the first gate comprises forming a polycrystalline semiconductor layer over the substrate and reacting the polycrystalline semiconductor layer with a metal such that the first gate consists essentially of an alloy of the metal and the semiconductor layer.
75. The method of claim 62 wherein the first transistor is disposed in a chip, the method further comprising:
- attaching the chip to a package,
- wherein at least a portion of the stress in the first channel region is induced by the package.
76. The method of claim 64 wherein the first stress-inducing element comprises a metal-semiconductor alloy formed over at least one of the first source region and the first drain region.
77. A method for forming a semiconductor structure, the method comprising:
- providing a substrate comprising a stressed layer having a first type of stress;
- forming a masking layer over the substrate such that the masking layer exerts a second type of stress on the stressed layer;
- removing the masking layer over a first portion of the substrate; and
- etching a trench in the first portion of the substrate.
78. The method of claim 77 wherein the first type of stress and the second type of stress are different.
79. The method of claim 77 wherein the masking layer comprises silicon nitride.
80. The method of claim 77, further comprising forming a pad oxide layer over the substrate prior to forming the masking layer.
81. A structure comprising:
- a substrate;
- a first transistor disposed over a first region of the substrate, the first transistor including: a first source region and a first drain region disposed in a first portion of the substrate, a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of strain, and a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; and
- a first trench structure disposed in a trench, wherein the trench is proximate at least one side of one of the first source region and the first drain region, the first trench structure inducing only a portion of the first type of strain in the first channel region.
82. The structure of claim 81, further comprising:
- a strained layer disposed over the substrate.
83. The structure of claim 82 wherein the strained layer comprises at least one of silicon and germanium.
84. The structure of claim 82 wherein at least a portion of the first channel region is disposed in the strained layer.
85. The structure of claim 82, further comprising:
- a dielectric layer disposed over the substrate,
- wherein the strained layer is disposed over and in contact with the dielectric layer.
86. The structure of claim 81 wherein the first type of strain is tensile.
87. The structure of claim 81 wherein the first type of strain is compressive.
88. The structure of claim 81 wherein the substrate comprises at least one of silicon and germanium.
89. The structure of claim 81 wherein the substrate comprises at least one element other than silicon.
90. The structure of claim 89 wherein the other element is germanium.
91. The structure of claim 81, further comprising:
- a first cap layer disposed over a surface of the first transistor,
- wherein the strain in the first channel region is induced by the first cap layer.
92. The structure of claim 91 wherein the first cap layer comprises silicon nitride.
93. The structure of claim 81 wherein the strain in the first channel region is induced by at least one of the first source region and the first drain region.
94. The structure of claim 93 wherein the at least one of the first source region and the first drain region comprises a second material having a larger lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
95. The structure of claim 94 wherein the second material comprises a material selected from the group consisting of SiGe and Ge.
96. The structure of claim 93 wherein the at least one of the first source region and the first drain region comprises a second material having a smaller lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
97. The structure of claim 96 wherein the second material comprises a material selected from the group consisting of SiGe, Si, and SiC.
98. The structure of claim 81 wherein the strain in the first channel region is induced by the first gate.
99. The structure of claim 98 wherein the first gate comprises material selected from the group consisting of metal silicide, metal germanosilicide, and metal germanocide.
100. The structure of claim 81, further comprising:
- a second transistor disposed over a second region of the substrate, the second transistor including: a second source region and a second drain region disposed in a second portion of the substrate, a second channel region disposed between the second source region and the second drain region, the second channel region having a second type of strain, and a second gate disposed above the second channel region and between the second source and second drain regions, the second gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; and
- a second trench structure disposed in a trench, wherein the trench is proximate at least one side of one of the second source region and the second drain region, the second trench structure inducing only a portion of the second type of strain in the second channel region.
101. The structure of claim 100 wherein the first and second types of strain are different.
102. The structure of claim 81 wherein the portion of the strain induced by the first trench structure is approximately zero.
103. The structure of claim 102, further comprising:
- a first strain-inducing element; and
- a first epitaxial strained layer,
- wherein the first channel region is disposed within a portion of the first epitaxial strained layer and the first strain-inducing element induces only a portion of the strain in the first channel region.
104. The structure of claim 103 wherein the first strain-inducing element comprises a first cap layer disposed over a surface of the first transistor.
105. The structure of claim 103 wherein the first strain-inducing element comprises the first gate.
106. The structure of claim 103 wherein the first strain-inducing element comprises at least one of the first source region and the first drain region.
107. A method for forming a semiconductor structure, the method comprising:
- providing a substrate;
- forming a first transistor over a first region of the substrate by: defining a first source region and a first drain region in a first portion of the substrate, defining a first channel region between the first source region and the first drain region, the first channel region having a first type of strain, and forming a first gate above the first channel region and between the first source and first drain regions, the first gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound;
- forming a first trench proximate at least one side of one of the first source region and the first drain region; and
- forming a first trench structure in the first trench, the first trench structure tailored to induce only a portion of the first type of strain in the first channel region.
108. The method of claim 107, further comprising:
- forming a second transistor over a second region of the substrate by: defining a second source region and a second drain region in a second portion of the substrate, defining a second channel region between the second source region and the second drain region, the second channel region having a second type of strain, and forming a second gate above the second channel region and between the second source and second drain regions, the second gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound;
- forming a second trench proximate at least one side of one of the second source region and the second drain region; and
- forming a second trench structure in the second trench, the second trench structure tailored to induce only a portion of the second type of strain in the second channel region.
109. The method of claim 108 wherein the first and second types of strain are different.
110. The method of claim 107, further comprising:
- forming a first cap layer over a surface of the first transistor, the cap layer tailored to induce the first type of strain in the first channel region.
111. The method of claim 107 wherein at least a portion of the strain in the first channel region is induced by at least one of the first source region and the first drain region.
112. The method of claim 111 wherein the at least one of the first source region and the first drain region comprises a second material having a larger lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
113. The method of claim 111 wherein the at least one of the first source region and the first drain region comprises a second material having a smaller lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
114. The method of claim 107 wherein at least a portion of the strain in the first channel region is induced by the first gate.
115. The method of claim 107 wherein the portion of the first type of strain the first trench structure is tailored to induce is approximately zero.
116. The method of claim 115 wherein the first channel region is defined in a portion of a first epitaxial strained layer.
117. The method of claim 115, further comprising:
- providing a first strain-inducing element.
118. The method of claim 117 wherein the first strain-inducing element comprises a first cap layer disposed over a surface of the first transistor.
119. The method of claim 117 wherein the first strain-inducing element comprises the first gate.
120. The method of claim 117 wherein the first strain-inducing element comprises at least one of the first source region and the first drain region.
121. A structure comprising:
- a substrate;
- a first transistor disposed over a first region of the substrate, the first transistor including: a first source region and a first drain region disposed in a first portion of the substrate, a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of stress, and a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; and
- a first trench structure disposed in a trench, wherein the trench is proximate at least one side of one of the first source region and the first drain region, the first trench structure inducing only a portion of the first type of stress in the first channel region.
122. The structure of claim 121, further comprising:
- a stressed layer disposed over the substrate.
123. The structure of claim 122 wherein the stressed layer comprises at least one of silicon and germanium.
124. The structure of claim 122 wherein at least a portion of the first channel region is disposed in the stressed layer.
125. The structure of claim 122, further comprising:
- a dielectric layer disposed over the substrate,
- wherein the stressed layer is disposed over and in contact with the dielectric layer.
126. The structure of claim 121 wherein the first type of stress is tensile.
127. The structure of claim 121 wherein the first type of stress is compressive.
128. The structure of claim 121 wherein the substrate comprises at least one of silicon and germanium.
129. The structure of claim 121 wherein the substrate comprises at least one element other than silicon.
130. The structure of claim 129 wherein the other element is germanium.
131. The structure of claim 121, further comprising:
- a first cap layer disposed over a surface of the first transistor,
- wherein the stress in the first channel region is induced by the first cap layer.
132. The structure of claim 131 wherein the first cap layer comprises silicon nitride.
133. The structure of claim 121 wherein the stress in the first channel region is induced by at least one of the first source region and the first drain region.
134. The structure of claim 133 wherein the at least one of the first source region and the first drain region comprises a second material having a larger lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
135. The structure of claim 134 wherein the second material comprises a material selected from the group consisting of SiGe and Ge.
136. The structure of claim 133 wherein the at least one of the first source region and the first drain region comprises a second material having a smaller lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
137. The structure of claim 136 wherein the second material comprises a material selected from the group consisting of SiGe, Si, and SiC.
138. The structure of claim 121 wherein the stress in the first channel region is induced by the first gate.
139. The structure of claim 138 wherein the first gate comprises material selected from the group consisting of metal silicide, metal germanosilicide, and metal germanocide.
140. The structure of claim 121, further comprising:
- a second transistor disposed over a second region of the substrate, the second transistor including: a second source region and a second drain region disposed in a second portion of the substrate, a second channel region disposed between the second source region and the second drain region, the second channel region having a second type of stress, and a second gate disposed above the second channel region and between the second source and second drain regions, the second gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound; and
- a second trench structure disposed in a trench, wherein the trench is proximate at least one side of one of the second source region and the second drain region, the second trench structure inducing only a portion of the second type of stress in the second channel region.
141. The structure of claim 140 wherein the first and second types of stress are different.
142. The structure of claim 121 wherein the portion of the stress induced by the first trench structure is approximately zero.
143. The structure of claim 142, further comprising:
- a first stress-inducing element; and
- a first epitaxial stressed layer,
- wherein the first channel region is disposed within a portion of the first epitaxial stressed layer and the first stress-inducing element induces only a portion of the stress in the first channel region.
144. The structure of claim 143 wherein the first stress-inducing element comprises a first cap layer disposed over a surface of the first transistor.
145. The structure of claim 143 wherein the first stress-inducing element comprises the first gate.
146. The structure of claim 143 wherein the first stress-inducing element comprises at least one of the first source region and the first drain region.
147. A method for forming a semiconductor structure, the method comprising:
- providing a substrate;
- forming a first transistor over a first region of the substrate by: defining a first source region and a first drain region in a first portion of the substrate, defining a first channel region between the first source region and the first drain region, the first channel region having a first type of stress, and forming a first gate above the first channel region and between the first source and first drain regions, the first gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound;
- forming a first trench proximate at least one side of one of the first source region and the first drain region; and
- forming a first trench structure in the first trench, the first trench structure tailored to induce only a portion of the first type of stress in the first channel region.
148. The method of claim 147, further comprising:
- forming a second transistor over a second region of the substrate by: defining a second source region and a second drain region in a second portion of the substrate, defining a second channel region between the second source region and the second drain region, the second channel region having a second type of stress, and forming a second gate above the second channel region and between the second source and second drain regions, the second gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound;
- forming a second trench proximate at least one side of one of the second source region and the second drain region; and
- forming a second trench structure in the second trench, the second trench structure tailored to induce only a portion of the second type of stress in the second channel region.
149. The method of claim 148 wherein the first and second types of stress are different.
150. The method of claim 147, further comprising:
- forming a first cap layer over a surface of the first transistor, the cap layer tailored to induce the first type of stress in the first channel region.
151. The method of claim 147 wherein at least a portion of the stress in the first channel region is induced by at least one of the first source region and the first drain region.
152. The method of claim 151 wherein the at least one of the first source region and the first drain region comprises a second material having a larger lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
153. The method of claim 151 wherein the at least one of the first source region and the first drain region comprises a second material having a smaller lattice constant than a lattice constant of a semiconductor material disposed in at least one of the first channel region and an area proximate at least one of the first source region and the first drain region.
154. The method of claim 147 wherein at least a portion of the stress in the first channel region is induced by the first gate.
155. The method of claim 147 wherein the portion of the first type of stress the first trench structure is tailored to induce is approximately zero.
156. The method of claim 155 wherein the first channel region is defined in a portion of a first epitaxial stressed layer.
157. The method of claim 155, further comprising:
- providing a first stress-inducing element.
158. The method of claim 157 wherein the first stress-inducing element comprises a first cap layer disposed over a surface of the first transistor.
159. The method of claim 157 wherein the first stress-inducing element comprises the first gate.
160. The method of claim 157 wherein the first stress-inducing element comprises at least one of the first source region and the first drain region.
Type: Application
Filed: Sep 22, 2006
Publication Date: Jan 18, 2007
Inventors: Qing Ma (San Jose, CA), Jin Lee (Mountain View, CA), Harry Fujimoto (Sunnyvale, CA), Changhong Dai (San Jose, CA), Shiuh-Wuu Lee (San Jose, CA), Travis Eiles (San Jose, CA), Krishna Seshan (San Jose, CA)
Application Number: 11/525,982
International Classification: H01L 29/00 (20060101);