Patents by Inventor Travis Reynold Hebig

Travis Reynold Hebig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170206948
    Abstract: Encoded bitlines run globally through a memory architecture. The encoded bitlines carry an encoded representation of the data bits read from memory cells. As a specific example, the encoded representation may be carried on encoded global bitlines in an SRAM memory architecture. The encoded representation reduces power consumption when used in conjunction with bitline pre-charging or pre-discharging. The encoding technique may be implemented in circuitry other than memories and applied to any type of signal bus, e.g., for address, data, or control signals, running between any types of circuitry.
    Type: Application
    Filed: January 21, 2016
    Publication date: July 20, 2017
    Inventors: Travis Reynold Hebig, Ronald Daniel lsliefson, Carl Anthony Monzel, III, Myron James Buer
  • Patent number: 8860141
    Abstract: A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Michael Launsbach, Daniel Mark Nelson
  • Patent number: 8467261
    Abstract: A method and circuit are provided for implementing smart switched decoupling capacitors to efficiently reduce power supply noise in a logic circuit, and a design structure on which the subject circuit resides. The logic circuit includes a logic macro, a high-current event control signal activating a logic function, and a switched decoupling capacitor circuit integrated within the logic macro. The switched decoupling capacitor circuit uses the high-current event control signal to control capacitor switching to discharge to a voltage supply rail responsive to activating the logic function, and to charge the capacitors.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: Travis Reynold Hebig, David Paul Paulsen
  • Patent number: 8467230
    Abstract: A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Michael Launsbach, Daniel Mark Nelson
  • Patent number: 8159260
    Abstract: A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: April 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Daniel Mark Nelson
  • Publication number: 20120087176
    Abstract: A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.
    Type: Application
    Filed: October 6, 2010
    Publication date: April 12, 2012
    Applicant: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Michael Launsbach, Daniel Mark Nelson
  • Publication number: 20120081143
    Abstract: A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Daniel Mark Nelson
  • Publication number: 20120008443
    Abstract: A method and circuit are provided for implementing smart switched decoupling capacitors to efficiently reduce power supply noise in a logic circuit, and a design structure on which the subject circuit resides. The logic circuit includes a logic macro, a high-current event control signal activating a logic function, and a switched decoupling capacitor circuit integrated within the logic macro. The switched decoupling capacitor circuit uses the high-current event control signal to control capacitor switching to discharge to a voltage supply rail responsive to activating the logic function, and to charge the capacitors.
    Type: Application
    Filed: July 9, 2010
    Publication date: January 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Travis Reynold Hebig, David Paul Paulsen
  • Patent number: 7924633
    Abstract: A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Daniel Mark Nelson
  • Patent number: 7911827
    Abstract: An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: March 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
  • Patent number: 7835176
    Abstract: A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chad Allen Adams, Todd Alan Christensen, Peter Thomas Freiburger, Travis Reynold Hebig
  • Patent number: 7788554
    Abstract: A design structure embodied in a machine readable medium for implementing static random access memory (SRAM) cell write performance evaluation is provided. A SRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chad Allen Adams, Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson
  • Publication number: 20100214859
    Abstract: A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 26, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derick Gardner Behrends, Todd Alan Christensen, Travis Reynold Hebig, Daniel Mark Nelson
  • Patent number: 7768851
    Abstract: A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chad Allen Adams, Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson
  • Publication number: 20100188886
    Abstract: An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 29, 2010
    Applicant: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
  • Publication number: 20100188888
    Abstract: A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 29, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chad Allen Adams, Todd Alan Christensen, Peter Thomas Freiburger, Travis Reynold Hebig
  • Patent number: 7737757
    Abstract: Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
  • Patent number: 7724585
    Abstract: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
  • Publication number: 20100118621
    Abstract: A method and signal timing adjustment circuit for implementing variation tolerant memory array signal timing, and a design structure on which the subject circuit resides are provided. A logic circuit generates a first delay signal based upon logic devices forming the logic circuit. A memory cell circuit receives the first delay signal and generates control signals responsive to the first delay signal and based upon memory cell devices forming the memory cell circuit. A programmable logic delay circuit receives the control signals and generates a timing adjustment signal.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 13, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chad Allen Adams, Derick Gardner Behrends, Travis Reynold Hebig
  • Patent number: 7684263
    Abstract: A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base blocks includes a SRAM cell, such as an eight-transistor (8T) static random access memory (SRAM) cell, and a local evaluation block coupled to the SRAM cell. The SRAM cell includes independent left wordline input and right wordline input. The SRAM cell includes a read wordline connected high, and a true and complement write bitline pair connected low. In the local evaluation circuit, one input of a NAND gate receiving the read bitline input is connected high. A control signal is combined with an inverted feedback signal to start and stop the ring oscillator.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chad Allen Adams, Todd Alan Christensen, Peter Thomas Freiburger, Travis Reynold Hebig