DELAY CHAIN BURN-IN FOR INCREASED REPEATABILITY OF PHYSICALLY UNCLONABLE FUNCTIONS
A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.
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1. Technical Field
This disclosure generally relates to physically unclonable functions, and more specifically relates to burn-in of delay chains for increased repeatability of physically unclonable functions.
2. Background Art
For security reasons, it is desirable to implement physically unclonable functions (PUF) in integrated circuits. A PUF is an electrical circuit function that is difficult to characterize and clone. A PUF is useful for challenge-response authentication type security in electronic systems. The PUF can be used in electronic systems to obtain different functions or security keys in two chips where the differences in the two chips are physically undetectable. Each PUF device has a unique and unpredictable way of mapping challenges to responses.
A silicon or physical PUF exploits random variations in a circuit produced during the manufacturing of the circuit device. The PUF circuit can use these random variations in the delay of circuit components to achieve an unpredictable mapping of challenges and responses. For example, given an input challenge, a race condition is set up in the circuit, and two transitions that propagate along different paths are compared to see which comes first. An arbiter, typically implemented as a latch, produces a logical “1” or a “0”, depending on which transition comes first. When a circuit with the same layout mask is fabricated on different chips, the logic function implemented by the circuit is different for each chip due to the random variations of delays. To achieve repeatability, the random delay needs to be greater than the sensitivity of the arbiter. If the random process variation does not cause a statistically reliable difference in the delay of the paths, then the PUF will have low repeatability. This means that variation in temperature, voltage, and other factors can change the response of the system and thus the challenge response of the circuit will not be useful due to low repeatability.
BRIEF SUMMARYThe disclosure is directed to a circuit and method for increasing the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit is used to hold the inputs of the two delay chains at opposite random values during the burn-in process such that one delay chain is held at one random state and the other delay chain is held at the opposite random state. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage due to the known phenomenon of Negative Biased Temperature Instability (NBTI). Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.
The foregoing and other features and advantages will be apparent from the following more particular description, as illustrated in the accompanying drawings.
The disclosure will be described in conjunction with the appended drawings, where like designations denote like elements, and:
Described herein is an apparatus and method for increasing the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit is used to hold the inputs of the two delay chains at opposite random values during the burn-in process such that one delay chain is held at one random state and the other delay chain is held at the opposite random state. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage due to the known phenomenon of Negative Biased Temperature Instability (NBTI). Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.
As described in the background, a PUF circuit can use random variations in the delay of circuit components to achieve an unpredictable mapping of challenges and responses. However, where the random process variation does not cause a statistically reliable difference in the delay of the paths, then the PUF will have low repeatability.
Referring again to
The challenge/response mode of the circuit shown in
The modes of operation are summarized in Table 1 with the inputs on Challenge_Clk, Burn_In and Random_Data as shown.
Negative biased temperature instability (NBTI) is a reliability concern with p-type CMOS devices. It manifests itself as an increase in the threshold voltage required to turn on a PFET device. The degradation of NBTI devices decreases exponentially over time. Manufactured integrated circuits often undergo a burn-in procedure that stresses the part to screen out the initial degradation of the parts. A PFET that has a static state of “0” on it's input during chip burn-in is stressed due to NBTI which causes it's turn on voltage (Vt) to be permanently elevated. PFETs with elevated Vt are slower to turn on. The circuit described above utilizes the phenomenon of NBTI and the burn-in procedure to enhance the variation of signal delay through two delay chains to increase the repeatability of the PUF circuit.
One skilled in the art will appreciate that many variations are possible within the scope of the claims. While the examples herein are described in terms of time, these other types of thresholds are expressly intended to be included within the scope of the claims. Thus, while the disclosure is particularly shown and described above, it will be understood by those skilled in the art that these and other changes in form and details may be made therein without departing from the spirit and scope of the claims.
Claims
1) An electronic circuit comprising:
- a first delay chain and a second delay chain each having inputs and outputs;
- a burn-in circuit that places the electronic circuit in a burn-in mode and places a random input bit on the input of the first delay chain and places an inverse of the random input bit on the input of the second delay chain and holds these inputs of the first and second delay chains while the circuit is burned in; and
- an arbiter circuit connected to the outputs of the first and second delay chains to output a “0” or a “1” depending on which delay chain is faster when a challenge bit is applied at the inputs of first and second delay chains.
2) (canceled)
3) The electronic circuit of claim 1 wherein the outputs of the delay chains connected to the arbiter provide for a challenge/response of physically unclonable function.
4) The electronic circuit of claim 1 wherein the arbiter circuit is a latch that detects which of the first and second delay chains transitions first after receiving a challenge input.
5) The electronic circuit of claim 1 wherein the circuit burn-in includes burning-in an entire integrated circuit containing the first and second delay chains.
6) The electronic circuit of claim 1 wherein the first and second delay chains are a chain of complementary metal-oxide semiconductor (CMOS) inverters.
7) The electronic circuit of claim 1 wherein the first and second delay chains are a chain of complementary metal-oxide semiconductor (CMOS) NAND gates.
8) The electronic circuit of claim 1 wherein the burn-in circuit comprises:
- a first and second NAND gate, with the first NAND gate having an output connected to the first delay chain, the second NAND gate having an output connected to the second delay chain, and a challenge_clk signal connected to a first input of the first and second NAND gates, wherein the output of the first and second NAND gates provide the random bit and the inverse of the random bit on the inputs of the delay chains;
- a third and fourth NAND gate, with the third NAND gate having an output connected to a second input of the first NAND gate and the fourth NAND gate having an output connected to a second input of the second NAND gate;
- a burn-in signal connected to a first input of the third and fourth NAND gates; and
- a random data signal connected to a second input of the fourth NAND gate and connected to a second input of the third NAND gate through an inverter.
9) An electronic circuit comprising:
- a first delay chain and a second delay chain each having inputs and outputs, wherein the first and second delay chains are a chain of complementary metal-oxide semiconductor (CMOS) inverters;
- a burn-in circuit that places the electronic circuit in a burn-in mode and places a random input bit on the input of the first delay chain and places an inverse of the random input bit on the input of the second delay chain and holds these inputs of the first and second delay chains while the circuit is burned in;
- a latch connected to the outputs of the first and second delay chains to output a “0” or a “1” depending on which delay chain is faster when a challenge bit is applied at the inputs of first and second delay chains, wherein the outputs of the delay chains connected to the arbiter provide for a challenge/response of physically unclonable function;
- wherein the burn-in circuit comprises: a first and second NAND gate, with the first NAND gate having an output connected to the first delay chain, the second NAND gate having an output connected to the second delay chain, and a challenge_clk signal connected to a first input of the first and second NAND gates, wherein the output of the first and second NAND gates provide the random bit and the inverse of the random bit on the inputs of the delay chains; a third and fourth NAND gate, with the third NAND gate having an output connected to a second input of the first NAND gate and the fourth NAND gate having an output connected to a second input of the second NAND gate; a burn-in signal connected to a first input of the third and fourth NAND gates; and a random data signal connected to a second input of the fourth NAND gate and connected to a second input of the third NAND gate through an inverter.
10) A method for increased repeatability in physically unclonable functions by increasing the delay difference of delay chains in an integrated circuit, the method comprising the steps of:
- (A) generating a random bit;
- (B) applying the random bit to an input of a first delay chain and an inverse of the random bit to an input of a second delay chain;
- (C) performing burn-in on the first and second delay chains while maintaining the random bit and the inverse of the random bit at the inputs to the first and second delay chains; and
- (D) using outputs of the delay chains connected to an arbiter for a challenge/response of physically unclonable function.
11) (canceled)
12) The method of claim 10 wherein the arbiter is a latch that detects which of the first and second delay chains transitions first after receiving a challenge input.
13) The method of claim 10 wherein the step of performing burn-in includes burning-in an entire integrated circuit containing the first and second delay chains.
14) The method of claim 10 wherein the first and second delay chains are a chain of complementary metal-oxide semiconductor (CMOS) inverters.
15) The method of claim 10 wherein the first and second delay chains are a chain of complementary metal-oxide semiconductor (CMOS) NAND gates.
Type: Application
Filed: Oct 5, 2010
Publication Date: Apr 5, 2012
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Derick Gardner Behrends (Rochester, MN), Todd Alan Christensen (Rochester, MN), Travis Reynold Hebig (Rochester, MN), Daniel Mark Nelson (Rochester, MN)
Application Number: 12/898,044
International Classification: H03K 19/00 (20060101);