Patents by Inventor Trevor Blyth
Trevor Blyth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8194015Abstract: The invention relates to an apparatus for electronic display comprising means for generating liquid-crystal-display (LCD) input signals, a LCD panel operable to display a color image according to the LCD input signals, a circuit operable to generate a plurality of sets of gamma correction values for gamma correction of the LCD input signals, and means for eliminating dependency of the plurality of sets of gamma correction values on a supply voltage (AVDD) of the circuit.Type: GrantFiled: February 26, 2007Date of Patent: June 5, 2012Assignee: Alta Analog, Inc.Inventors: Richard V. Orlando, Trevor A. Blyth
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Patent number: 8188952Abstract: The present invention relates to a method and a system of reducing flicker in a liquid crystal display (LCD). The LCD produces a display based on a video signal. A gamma curve of the LCD includes multiple gamma reference voltages corresponding to multiple gray scale values of the video signal. The method (and a system implementing the method) includes determining the gamma curve of the LCD for producing a predetermined luminance performance, driving the LCD by a test pattern having one of the multiple gray scale values, measuring a flicker of the LCD driven by the test pattern, and adjusting a gamma reference voltage in the gamma curve based on the flicker measurement to minimize the flicker of the LCD where the gamma reference voltage corresponds to the gray scale value in the gamma curve.Type: GrantFiled: November 8, 2007Date of Patent: May 29, 2012Assignee: Alta Analog, Inc.Inventors: Richard V. Orlando, Trevor A. Blyth
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Patent number: 7557788Abstract: A programmable buffer integrated circuit which can be programmed to output a set of gamma correction reference voltages to be used in LCD displays. Once programmed, the buffers will continuously output the programmed value. The device incorporates a programming interface to allow the programming of the buffer outputs to the desired values during manufacturing and test of the panel. Multiple sets of values can be programmed to provide different gamma correction curves for different user or application requirements.Type: GrantFiled: May 1, 2007Date of Patent: July 7, 2009Assignee: Alta Analog, Inc.Inventors: Richard V. Orlando, Trevor A. Blyth
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Patent number: 7554843Abstract: A serial bus which comprises two wires (a clock signal and a data signal), one of which transmits high voltages in addition to the two-level voltages used for conventional serial digital data transmission. During the second part of the transmission one of the serial wires changes function to a high voltage signal that is used to program the location which was addressed in the first part of the transmission. The high voltage signal may be a simple DC level for programming digital data into memory, or it can be a set of pulses with either fixed or variable parameters for programming digital, multi-level or analog levels into memory.Type: GrantFiled: November 4, 2005Date of Patent: June 30, 2009Assignee: Alta Analog, Inc.Inventors: Trevor A. Blyth, Richard V. Orlando
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Patent number: 7233305Abstract: A programmable buffer integrated circuit which can be programmed to output a set of gamma correction reference voltages to be used in LCD displays. Once programmed, the buffers will continuously output the programmed value. The device incorporates a programming interface to allow the programming of the buffer outputs to the desired values during manufacturing and test of the panel. Multiple sets of values can be programmed to provide different gamma correction curves for different user or application requirements.Type: GrantFiled: December 23, 2003Date of Patent: June 19, 2007Assignee: Alta Analog, Inc.Inventors: Richard V. Orlando, Trevor A. Blyth
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Patent number: 7071763Abstract: A switching circuit is disclosed for switching high voltages and high currents, if necessary, without causing snapback or breakdown. The disclosed high voltage, high current switching circuit comprises a first set of series-connected transistors that includes a plurality of transistors to switch a high voltage without inducing snapback or breakdown; and a second set of series-connected transistors that includes one or more transistors to switch a high current. The first and second sets of series-connected transistors are connected in parallel. The gates of the second set of series-connected transistors are enabled to cause conduction through the second set of series-connected transistors. In addition, a voltage detector is connected to an output of the first and second sets of series-connected transistors. The output of the voltage detector is coupled to the enabling means.Type: GrantFiled: March 3, 2003Date of Patent: July 4, 2006Assignee: Emosyn America, Inc.Inventor: Trevor Blyth
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Patent number: 7061380Abstract: A single integrated circuit provides communication, sensing and recording of one or more conditions critical to the entity to which it is attached. The chip is part of a larger module comprising a visual indicator, such as an LED, and a power source such as a battery. The sensor may be a temperature sensor whose output is stored in a non-volatile memory section of the chip on some periodic basis. A product identifier is stored on the chip; a method for product recall or location is described.Type: GrantFiled: November 5, 2003Date of Patent: June 13, 2006Assignee: Alta Analog, Inc.Inventors: Richard V. Orlando, Trevor A. Blyth
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Patent number: 6985372Abstract: The invention discloses an analog content addressable memory (CAM) that employs analog storage cells with programmable analog transfer function capability. The analog CAM scans and/or compares its memory array contents to determine if an analog voltage applied at Vin matches a value stored in the memory array. If the value applied to Vin matches a value stored in the analog CAM, the analog data stored at a different and corresponding location in an analog storage cell is coupled to the Vout output. An analog content addressable memory, comprising a first array A of analog memory cells for storing and generating a VA voltage; and a comparator having a first input for receiving a Vin voltage, a second input for receiving the VA voltage from the first array A of analog memory cells. Analog-to-Digital and Digital-to-Analog Converters comprising an array of analog memory cells.Type: GrantFiled: April 17, 2003Date of Patent: January 10, 2006Assignee: Alta Analog, Inc.Inventors: Trevor A. Blyth, Richard V. Orlando
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Patent number: 6950336Abstract: An emulated EEPROM memory array is disclosed based on non-volatile floating gate memory cells, such as Flash cells, where a small group of bits share a common source line and common row lines, so that the small group of bits may be treated as a group during program and erase modes to control the issues of program disturb and effective endurance. The bits common to the shared source line make up the emulated EEPROM page which is the smallest unit that can be erased and reprogrammed, without disturbing other bits. The memory array is physically divided up into groups of columns. One embodiment employs four memory arrays, each consisting of 32 columns and 512 page rows (all four arrays providing a total of 1024 pages with each page having 8 bytes or 64 bits). A global row decoder decodes the major rows and a page row driver and a page source driver enable the individual rows and sources that make up a given array.Type: GrantFiled: January 10, 2003Date of Patent: September 27, 2005Assignee: Emosyn America, Inc.Inventors: David Sowards, Trevor Blyth, Shane C. Hollmer
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Publication number: 20040125524Abstract: A switching circuit is disclosed for switching high voltages and high currents, if necessary, without causing snapback or breakdown. The disclosed high voltage, high current switching circuit comprises a first set of series-connected transistors that includes a plurality of transistors to switch a high voltage without inducing snapback or breakdown; and a second set of series-connected transistors that includes one or more transistors to switch a high current. The first and second sets of series-connected transistors are connected in parallel. The gates of the second set of series-connected transistors are enabled to cause conduction through the second set of series-connected transistors. In addition, a voltage detector is connected to an output of the first and second sets of series-connected transistors. The output of the voltage detector is coupled to the enabling means.Type: ApplicationFiled: March 3, 2003Publication date: July 1, 2004Inventor: Trevor Blyth
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Patent number: 6693828Abstract: Reference voltages are disclosed for storage in addition to the analog or digital information for reconstructing the original voltage value of one or more analog or digital signals in non-volatile memory cells. The reference voltages are stored in separate memory cells and are written at the same time as the target information. The target information may be a single analog voltage, multiple analog voltages or a burst of digital data and is written during a relatively short period of time during which the ambient conditions do not change significantly.Type: GrantFiled: April 17, 2003Date of Patent: February 17, 2004Assignee: Alta Analog, Inc.Inventors: Trevor A. Blyth, Richard V. Orlando
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Publication number: 20030189858Abstract: An emulated EEPROM memory array is disclosed based on non-volatile floating gate memory cells, such as Flash cells, where a small group of bits share a common source line and common row lines, so that the small group of bits may be treated as a group during program and erase modes to control the issues of program disturb and effective endurance. The bits common to the shared source line make up the emulated EEPROM page which is the smallest unit that can be erased and reprogrammed, without disturbing other bits. The memory array is physically divided up into groups of columns. One embodiment employs four memory arrays, each consisting of 32 columns and 512 page rows (all four arrays providing a total of 1024 pages with each page having 8 bytes or 64 bits). A global row decoder decodes the major rows and a page row driver and a page source driver enable the individual rows and sources that make up a given array.Type: ApplicationFiled: January 10, 2003Publication date: October 9, 2003Inventors: David Sowards, Trevor Blyth, Shane C. Hollmer
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Patent number: 6510081Abstract: By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.Type: GrantFiled: December 18, 2001Date of Patent: January 21, 2003Assignee: Advanced Technology Materials, Inc.Inventors: Trevor Blyth, David Sowards, Philip C. Barnett
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Patent number: 6466488Abstract: A logic level detection circuit that includes a sense amplifier and a consumption equilibration circuit that is topologically distinct from the sense amplifier and that reduces and/or substantially eliminates data dependent electrical consumption by having a data dependent electrical consumption that compensates the data dependent electrical consumption of the sense amplifier. The sense amplifier may be implemented as a current-sensing sense amplifier, and the consumption equilibration circuit may be implemented as a selectively enabled current source that is responsive to a signal generated by the current-sensing sense amplifier. The consumption equilibration circuit may be implemented with a small number of transistors and in a small chip area compared to the number of transistors and chip area used for implementing the sense amplifier.Type: GrantFiled: March 8, 2001Date of Patent: October 15, 2002Assignee: Advanced Technology Materials, Inc.Inventors: David Sowards, Trevor Blyth
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Publication number: 20020114185Abstract: By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.Type: ApplicationFiled: December 18, 2001Publication date: August 22, 2002Inventors: Trevor Blyth, David Sowards, Philip C. Barnett
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Patent number: 6437627Abstract: A high voltage level shifter utilizing only low voltage PMOS and low voltage NMOS devices. The high voltage level shifter is used to distribute the high voltage almost equally among the PMOS devices and almost equally among the NMOS devices to meet the device electrical specification of low voltage MOS devices for various breakdown mechanisms. A layout technique is also used to achieve a much higher junction breakdown of N+ drain to P-substrate and a better gated diode breakdown of NMOS devices.Type: GrantFiled: August 25, 1995Date of Patent: August 20, 2002Assignee: Winbond Electronics CorporationInventors: Hieu Van Tran, Trevor Blyth
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Patent number: 6421213Abstract: A system is disclosed for isolating a bond pad from the rest of the circuitry of a semiconductor chip in a manner that protects the chip from applied signals that are outside the normal operating range and which tamper with the operation of the system. The system includes the use of a controllable switch for routing the signal from the bond pad to the circuit and a detector for detecting a tamper condition on the bond pad. The detection of a tamper condition causes the detector to inform the microcontroller on the chip to, for example, terminate the operation in progress, perform a controlled system shutdown, disable pre-arranged functions, or record the fact that a tamper condition occurred.Type: GrantFiled: March 17, 2000Date of Patent: July 16, 2002Assignee: Advanced Technology Materials, Inc.Inventor: Trevor A. Blyth
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Patent number: 6400603Abstract: By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.Type: GrantFiled: May 3, 2000Date of Patent: June 4, 2002Assignee: Advanced Technology Materials, Inc.Inventors: Trevor Blyth, David Sowards, Dean Allum, Philip C. Barnett
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Publication number: 20010038563Abstract: A logic level detection circuit that includes a sense amplifier and a consumption equilibration circuit that is topologically distinct from the sense amplifier and that reduces and/or substantially eliminates data dependent electrical consumption by having a data dependent electrical consumption that compensates the data dependent electrical consumption of the sense amplifier. The sense amplifier may be implemented as a current-sensing sense amplifier, and the consumption equilibration circuit may be implemented as a selectively enabled current source that is responsive to a signal generated by the current-sensing sense amplifier. The consumption equilibration circuit may be implemented with a small number of transistors and in a small chip area compared to the number of transistors and chip area used for implementing the sense amplifier.Type: ApplicationFiled: March 8, 2001Publication date: November 8, 2001Applicant: Advanced Technology Materials, Inc.Inventors: David Sowards, Trevor Blyth
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Patent number: 6219291Abstract: A logic level detection circuit that includes a sense amplifier and a consumption equilibration circuit that is topologically distinct from the sense amplifier and that reduces and/or substantially eliminates data dependent electrical consumption by having a data dependent electrical consumption that compensates the data dependent electrical consumption of the sense amplifier. The sense amplifier may be implemented as a current-sensing sense amplifier, and the consumption equilibration circuit may be implemented as a selectively enabled current source that is responsive to a signal generated by the current-sensing sense amplifier. The consumption equilibration circuit may be implemented with a small number of transistors and in a small chip area compared to the number of transistors and chip area used for implementing the sense amplifier.Type: GrantFiled: May 1, 2000Date of Patent: April 17, 2001Assignee: Advanced Technology Materials, Inc.Inventors: David Sowards, Trevor Blyth