Serial bus incorporating high voltage programming signals
A serial bus which comprises two wires (a clock signal and a data signal), one of which transmits high voltages in addition to the two-level voltages used for conventional serial digital data transmission. During the second part of the transmission one of the serial wires changes function to a high voltage signal that is used to program the location which was addressed in the first part of the transmission. The high voltage signal may be a simple DC level for programming digital data into memory, or it can be a set of pulses with either fixed or variable parameters for programming digital, multi-level or analog levels into memory.
Latest Alta Analog, Inc. Patents:
- Reduction of the effect of AVDD power supply variation on gamma reference voltages and the ability to compensate for manufacturing variations
- System and method for reducing LCD flicker
- Gamma reference voltage generator
- Gamma reference voltage generator
- Monitoring and recording tag with RF interface and indicator for fault event
The invention relates generally to the field of electronic circuits, and more particularly to serial data communication and the programming of non-volatile memory circuits.
DESCRIPTION OF RELATED ARTGenerally speaking, data communication between electronic components and sub-assemblies within an electronic system can be in either a parallel or a serial format. While serial communication has lower data rates or bandwidth compared to parallel systems, the main advantage of serial communication is the reduced number of wires and connection terminals. This results in smaller packages, fewer tracks on a printed circuit board and therefore reduced board area.
There are several different serial data communication protocols. One example is described in U.S. Pat. No. 4,689,740, a “Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations”; generally known as the IIC (Inter-Integrated Circuit) bus. The IIC bus has two signals—a clock signal and a bi-directional data signal. Another protocol is the SPI (Serial Peripheral Interface), as described in the Motorola M68HC11 Reference Manual, 1988 Section 8. The SPI bus has four signals—slave select, clock, and two unidirectional data lines. In certain circumstances the two data lines may be connected to make a single bidirectional data line, thus reducing the number of wires to three. A common characteristic of both the IIC and the SPI bus is that communication between bus locations is via digital data and the signal levels correspond to either a logic “0” or a logic “1”.
In a system that includes a non-volatile memory (NVM) it is customary to use high voltages when writing data into the NVM. Some types of memory generate the high voltages internally and therefore do not need an external high voltage source. Other types of memory achieve reduced complexity and reduced die size by eliminating the internal high voltage generation circuits and use an external voltage source. In this case an extra interface wire is needed to connect the external source, as well as an extra pin on the memory package—a major disadvantage in a system which uses a serial bus to minimize connections.
The present invention relates to systems in which communication is via a serial bus and in which a location on the serial bus requires high voltages, such as for programming a NVM. There exists a need for a serial bus that requires a reduced number of total wires in the interface.
SUMMARY OF THE INVENTIONThe invention discloses a serial bus which comprises two wires (a clock signal and a data signal), one of which transmits high voltages in addition to the two-level voltages used for conventional serial digital data transmission. One of the wires is coupled to and sends a clock signal while the other wire is coupled to and sends a data signal. A high voltage signal can be transmitted in addition to either of these signals on either wire to couple to the location requiring a high voltage.
A serial communication is divided into two parts. The first part is a conventional data stream in which the data and clock signals transmit digital data using two voltage levels that correspond to logic “0” and “1” levels. Transmission during this first part typically comprises a reset, a command, an address and a data stream, or a combination of these. During the second part of the transmission one of the serial wires changes function to transmit a high voltage signal that is used to program the location requiring high voltages, such as a NVM, which was addressed in the first part of the transmission.
In one embodiment, the high voltage signal is used to program data into a non-volatile memory. In this embodiment, the high voltage signal may be a simple DC level for programming digital data into memory, or it may be a set of pulses with either fixed or variable parameters for programming digital, multi-level or analog levels into memory.
One technique that allows analog voltages to be programmed into the NVM, in one embodiment of the invention, requires the output of the analog memory to be read after a program pulse. A decision is then made whether to apply another program pulse and which parameters or characteristics of the pulse should be changed, if any. The decision-making circuits and the pulse shaping circuits may be included on-chip, on the same integrated circuit as the NVM, or may be placed off-chip to minimize complexity and die area of the NVM. In the latter case, where the pulse-shaping is performed off-chip, it is necessary to connect the output voltage, as read from the analog memory, to the external pulse-shaping circuits. A dedicated wire may be added to provide this connection or, alternatively, the analog voltage may be multiplexed onto one of the existing serial bus wires.
Another embodiment couples high voltage pulses of fixed parameters or a D.C. voltage onto the interface. Programming of multi-level or analog values is performed by on-chip shaping of the pulses actually applied to the NVM memory cells.
A schematic of the first embodiment of the present invention is shown in
It[DFI] is understood that in certain embodiments, the functions of the Bus Interface Logic as described herein may be performed by a CPU, such as in a microcontroller or embedded circuit.
An example of a serial communication in one embodiment of the invention is shown in the voltage waveform diagram of
Pulse C, which follows the first part of the communication, is a high voltage pulse that is used within the NVM to either program or erase a bit or a group of bits, depending on the command, address and data that was present during the first part of the communication. The parameters of pulse C can be chosen to satisfy the needs of the particular technology used to implement the NVM. For instance, the pulse required for a memory operation that makes use of Fowler-Nordheim tunneling is generally a high voltage pulse (say 14V) of fairly long duration (say 2 milliseconds) and should have a relatively slow ramp up time (say 0.5 milliseconds) to achieve optimum endurance. Fowler-Nordheim tunneling is used during the erase of typical Flash memories and used during both erase and program of EEPROM memories. In contrast, a write operation that makes use of Channel Hot Electron injection (CHE) would typically use a pulse which is shorter in duration (say 10 microseconds), with faster rise time (2 microseconds) and lower voltage amplitude (say 9V). CHE is used to program many types of Flash memory. In another embodiment, a write operation that makes use of Channel Initiated Secondary Electron injection (CHISEL) may be used. The specified voltages and times are typical values for non-volatile memories employing 0.25 um feature sizes. The specified values are for illustrative purposes and can be modified according to the technology used for the NVM.
In another embodiment, a Vpp input can be a D.C. level or pulses with default characteristics. Pulse shaping is performed on-chip to create the required programming conditions for the desired writing operation.
A single high voltage pulse C is shown in
In an alternative embodiment, the high voltage for programming may be provided by SDA instead of VPP. In this case SDA would be connected to both the input of the level shifter and the NVM; VPP would connect directly into the Bus Interface Logic and perform the clocking function only.
In addition, supplying any location on a serial bus with a different voltage from that of the logic level of the serial bus using the above described method is considered within the scope of the invention. Such locations comprise other types of memory, devices, cards, cables, displays and other peripherals.
In a further embodiment of the invention, where a location requires a lower voltage rather than a higher voltage than the logic level, the pulses during the second part of any erase or programming communication may be low voltage. In such an embodiment, a switching device may be added to the serial interface to prevent damage to such a location requiring low voltage during the first part of the communication, which is at the logic level.
It is further understood that where one or more devices requiring a non-logic voltage level are located on the same bus interface, a multiplexer or switching device may be used to implement sending the voltage pulses to the individual devices as required.
Alternatively, the Select signals to the Mux block may be generated by an independent circuit located either on the same integrated circuit substrate or in a separate location to reduce die size and complexity.
The serial interface shown in
The analog output, which is desired to be re-written, is prepared to be erased by Send Erase command+Address 510. A high voltage pulse is then transmitted on Vpp (Send Erase on Vpp) 515. The addressed analog storage cell in the ANVM is erased by Vpp and the resulting analog voltage read at the Aout terminal (Read Aout) when Vpp returns to a low voltage 520. If Aout≦(is less than) Vmax 525, in other words, if the analog output has not been sufficiently erased so as to be above the maximum voltage of the storage dynamic range, the erase is repeated by sending another pulse on Vpp. The sequence is repeated until Aout is equal to or greater than Vmax. The erase procedure can be completed by a single Vpp pulse if the pulse is of sufficient voltage amplitude and of sufficient duration. The programming sequence is started by Send Program command+Address for the desired analog output 530. Set Vpp pulse to initial values is transmitted on the Vpp signal 535. The parameters of a program pulse 535, or Send Program Pulse on Vpp 540, such as rise time, voltage amplitude and pulse duration, may be default values or may be calculated based on the difference between the measured voltage on Aout and Vtarget. After programming Read Aout 545 by measuring the voltage of the addressed analog output at the Aout pin after Vpp returns to a low level. If Aout≧(is greater than) Vtarget 550, Calculate new Vpp 555 and the program sequence is repeated until Aout is less than or equal to Vtarget. For improved precision and faster convergence the Vpp levels can begin at relatively high voltage and wide pulse widths and reduce to lower voltages and/or reduced pulse widths as Aout approaches Vtarget.
The writing method may be modified in several ways without departing from the spirit of the invention. An analog value may first be fully programmed and then erased in controlled increments or steps. Alternatively, the value may be adjusted simply by well-controlled erase or program pulses. Yet another alternative is to provide pulses of fixed characteristics or a D.C. level and perform pulse shaping with on-chip circuits. In such cases, the present invention allows the combination of digital control, high voltage programming and the reading of analog voltages along a serial bus.
A further embodiment is shown in
Foregoing described embodiments of the invention are provided as illustrations and descriptions. They are not intended to limit the invention to precise form described. In particular, it is contemplated that functional implementation of invention described herein may be implemented equivalently in hardware, software, firmware, and/or other available functional components or building blocks. Other variations and embodiments are possible in light of above teachings, and it is thus intended that the scope of invention not be limited by this Detailed Description, but rather by Claims following.
Claims
1. A serial interface apparatus comprising:
- a first and second input;
- the second input comprising a logic level signal and a non-logic level signal coupling to the input of a level shifter; and
- the second input also coupling to a location requiring a non-logic level signal;
- wherein the non-logic level signal comprises a voltage different from a logic level signal;
- wherein on the second input, a first part of communication comprises one or more logic level pulses, and a second part of communication comprises one or more non-logic level pulses;
- wherein on the second input, the non-logic level signal and the logic level signal provide different functions.
2. The serial interface of claim 1 wherein the logic level signal is either a clock or a serial data signal, and the non-logic signal is capable of performing a write operation in a non-volatile memory.
3. The serial interface of claim 1 wherein the serial interface comprises a bus interface logic for providing logic level data, control, and synchronization to the location requiring the voltage different from that of the logic level.
4. The serial interface of claim 3 wherein the first input couples directly to the bus interface logic.
5. The serial interface of claim 1, wherein the location requiring the voltage different from that of the logic level comprises a memory, a device, a peripheral, a card, a cable or a display.
6. A method for combining logic level signals with non-logic level signals in a serial interface comprising the steps:
- sending a first logic level signal on a first input;
- sending a non-logic level signal and a second logic level signal on a second input; and
- converting the non-logic level and the second logic signal on the second input to a third logic level signal using a level shifter;
- combining the first logic level signal and the third logic level signal in bus interface logic,
- wherein the non-logic level signal comprises a voltage different from a logic level;
- wherein on the second input, a first part of communication comprises one or more logic level pulses, and a second part of communication comprises one or more non-logic level pulses;
- wherein the first logic level signal, the second logic level signal and the non-logic level signal provide different functions.
7. The method of claim 6 wherein a bus interface logic using the first and second logic level signals provides data to and controls a location requiring a non-logic level signal.
8. The method of claim 6 wherein the location requiring a non-logic level signal comprises a memory, a device, a peripheral, a card, a cable or a display.
9. The method of claim 6 wherein the first logic level signal is either a clock or a serial data signal, and the second logic level signal is the other signal, and the non-logic signal is capable of performing a write operation in a non-volatile memory.
10. A method of serial communication comprising the steps:
- converting a non-logic level signal to a logic level signal using a level shifter producing a logic level reset signal;
- sending logic level input data; and
- sending one or more non-logic level voltage pulses on either a logic level clock input or a logic level serial data input to a location requiring the non-logic level voltage;
- wherein the logic level signal is a two level logic signal.
11. The method of claim 10 wherein one or more non-logic level voltage pulses are used to program or erase one or more bits.
12. The method of claim 10 wherein the location requiring the non-logic level voltage comprises a non-volatile memory.
13. The method of claim 12 wherein the non-volatile memory is implemented using Fowler-Nordheim tunneling, Channel Hot Electron injection, or a combination thereof.
14. The method of claim 10 wherein the non-logic level voltage pulses are followed by sending a reset signal.
15. A serial interface for an analog non-volatile memory apparatus comprising:
- a first and second input;
- the second input comprising a logic level signal and a non-logic level signal coupling to the input of a level shifter; and
- the second input also coupling to a location requiring a voltage different from a logic level; wherein on the second input, a first part of communication comprises one or more logic level pulses, and a second part of communication comprises one or more non-logic level pulses;
- wherein on the second input, the non-logic level signal and the logic level signal provide different functions.
16. The serial interface of claim 15 wherein the serial interface comprises a bus interface logic which controls and provides data to the analog non-volatile memory apparatus.
17. The serial interface of claim 15 wherein the non-volatile memory produces a set of one or more analog outputs.
18. The serial interface of claim 17 wherein the analog outputs can be read, erased, and programmed by an external system.
19. The serial interface of claim 17 wherein the analog outputs are coupled to a multiplexer coupling one of the analog outputs to an output pin.
20. The serial interface of claim 19 wherein the bus interface logic generates a signal that determines the output signal sent to the output pin.
21. The serial interface of claim 18 wherein the external system uses one or more high voltage pulses to erase and program the analog outputs.
22. The serial interface of claim 17 wherein the analog outputs are coupled to a multiplexer coupling one of analog outputs to a second multiplexer under control of the interface and the second multiplexer is coupled to the first input such that when a direction control signal changes state, a selected analog output from the analog outputs is transferred onto the first input.
23. A method of serial communication to program or erase an analog output of a non-volatile memory comprising the steps:
- converting a non-logic level signal to a logic level signal using a level shifter;
- producing a logic level reset signal;
- sending logic level input data; and
- sending one or more non-logic level voltage pulses on either a logic level clock input or a logic level serial data input to a location requiring the non-logic level voltage;
- wherein the logic level signal is a two level logic signal.
24. The method of claim 23 wherein the non-logic level voltage pulses are followed by sending a reset signal.
25. The method of claim 23 wherein the clock input or the data input coupling to the level shifter converts the non-logic voltage signal to a logic level signal for a bus interface logic which provides the data to and controls the analog output of the non-volatile memory.
26. A two wire serial interface bus comprising:
- a first wire and a second wire;
- the first wire comprises a first logic level signal; and
- the second wire comprises a non-logic level signal, and a second logic level signal, wherein the second wire is coupled to a level shifter and is also coupled to a location requiring a non-logic level signal; and
- a bus interface logic whose inputs are coupled from the output of the level shifter and from the first wire, the bus interface logic provides data and control information;
- wherein on the second input, a first part of communication comprises one or more logic level pulses, and a second part of communication comprises one or more non-logic level pulses;
- wherein the first logic level signal is either a clock signal or a serial data signal and the second logic level signal is the other signal;
- wherein the non-logic level signal is capable of performing a write operation in a non-volatile memory.
| 5301161 | April 5, 1994 | Landgraf et al. |
| 5467307 | November 14, 1995 | D'Arrigo et al. |
| 5532962 | July 2, 1996 | Auclair et al. |
| 5557569 | September 17, 1996 | Smayling et al. |
| 5694360 | December 2, 1997 | Iizuka et al. |
| 5828607 | October 27, 1998 | Bushey et al. |
| 6023427 | February 8, 2000 | Lakhani et al. |
| 6108262 | August 22, 2000 | Itoh et al. |
| 6166969 | December 26, 2000 | Song et al. |
| 6169687 | January 2, 2001 | Johnson |
| 6249458 | June 19, 2001 | Shokouhi et al. |
| 6269029 | July 31, 2001 | Suh |
| 6304495 | October 16, 2001 | Kim et al. |
| 6373773 | April 16, 2002 | Sumimoto |
| 6721212 | April 13, 2004 | Sasaki |
| 6807116 | October 19, 2004 | Yamazaki et al. |
| 6813185 | November 2, 2004 | Kobayashi et al. |
| 6826107 | November 30, 2004 | Dvir et al. |
| 6937496 | August 30, 2005 | Mizuno et al. |
| 6947332 | September 20, 2005 | Wallace et al. |
| 6947347 | September 20, 2005 | Fujioka |
| 6957135 | October 18, 2005 | Okada et al. |
| 6963501 | November 8, 2005 | Shiga |
| 6972977 | December 6, 2005 | Urabe |
| 7120061 | October 10, 2006 | Daga |
| 7209252 | April 24, 2007 | Owens et al. |
| 7230852 | June 12, 2007 | Mitani et al. |
| 7243185 | July 10, 2007 | See et al. |
| 7243856 | July 17, 2007 | Agami et al. |
| 7254083 | August 7, 2007 | Beckert et al. |
| 7259997 | August 21, 2007 | You |
| 7266017 | September 4, 2007 | Harari et al. |
| 7415680 | August 19, 2008 | Hoberman et al. |
Type: Grant
Filed: Nov 4, 2005
Date of Patent: Jun 30, 2009
Assignee: Alta Analog, Inc. (San Jose, CA)
Inventors: Trevor A. Blyth (Sandy, UT), Richard V. Orlando (Los Gatos, CA)
Primary Examiner: Trong Phan
Attorney: Fernandez & Associates, LLP
Application Number: 11/267,460
International Classification: G11C 11/34 (20060101);
