Abstract: In some embodiments, an antenna module includes an antenna element having a first side and a second side opposite the first side, the first side comprising a radiating side of the antenna element and a support structure disposed at the second side of the antenna element and configured to define a cavity, the support structure including a portion configured to reduce signal leakage between the antenna element and the cavity.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a package substrate, a die coupled to the package substrate, a photonics integrated circuit (PIC) coupled to the die, and a fiber array unit (FAU) optically coupled to the PIC. In an embodiment, the FAU has a base with a first width and a protrusion with a second width that is smaller than the first width.

Abstract: In some embodiments, an antenna module includes an antenna element having a first side and a second side opposite the first side, the first side comprising a radiating side of the antenna element and a support structure disposed at the second side of the antenna element and configured to define a cavity, the support structure including a portion configured to reduce signal leakage between the antenna element and the cavity.

Abstract: Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, a micro-ring resonator (MRR) over the second substrate, a heater integrated into the MRR, a cladding over the MRR, an opening through the first substrate and the second substrate to expose a bottom surface of the MRR, and a base spanning across the opening.

Abstract: Embodiments disclosed herein include an optoelectronic system. In an embodiment, the optoelectronic system comprises a first substrate, a second substrate over the first substrate, and a micro-ring resonator (MRR) over the second substrate. In an embodiment, a heater is integrated into the MRR, a cladding is over the MRR, and a temperature sensor is over the MRR in the cladding.

Abstract: Embodiments disclosed herein include an on-cavity photonic integrated circuit (OCPIC). In an embodiment, the OCPIC comprises a laser transmitter, that comprises a row with four bumps, and a micro-ring resonator (MRR) in the row between a first bump and a second bump of the four bumps. In an embodiment, a cavity is below the MRR, where a diameter of the cavity is substantially equal to a spacing between the first bump and the second bump.

Abstract: A system configured to assist blockchain-based Internet of Things (IoT) applications connect with one another and share data securely and privately is described. The system includes an IoT network configured to interact with a blockchain network. The IoT network includes IoT systems, which include IoT devices that comprise sensors. The blockchain network includes a mainchain and sidechains. Each sidechain includes a consensus protocol that run on each node and is configured to increase data and synchronization between nodes. The consensus protocol utilizes a reasoning mechanism to enable each node to deduce states of events on other nodes, a gossip algorithm to synchronize data between nodes, and a vector clock algorithm in a knowledge graph deployed on every node to allow the event created during synchronization to be linked to the previous two events.

Abstract: In some embodiments, a phased array antenna, includes a plurality of antenna modules arranged in an antenna lattice configuration to form the phased array antenna, wherein an antenna module of the plurality of antenna modules includes an antenna element packaged together with an amplifier.

Abstract: In some embodiments, an antenna module includes an antenna element having a first side and a second side opposite the first side, the first side comprising a radiating side of the antenna element and a support structure disposed at the second side of the antenna element and configured to define a cavity, the support structure including a portion configured to reduce signal leakage between the antenna element and the cavity.

Abstract: In some embodiments, a phased array antenna, includes a plurality of antenna modules arranged in an antenna lattice configuration to form the phased array antenna, wherein an antenna module of the plurality of antenna modules includes an antenna element packaged together with an amplifier.

Abstract: An integrated circuit having a transmitter is provided. The transmitter may include a serializer, a driver, and an associated calibration circuit. The calibration circuit may include a detector and a control circuit. The control circuit may output a first control signal for selectively configuring the serializer to inject test data and may also output a second control signal for selectively inverting the input polarity of the detector. The control circuit may configure the transmitter in at least four different modes by adjusting the first and second control signals. In each of the four modes, the control circuit may sweep a clock duty cycle correction (DCC) setting that controls only the serializer until the detector flips. Codes generated in this way may be used to compute calibrated settings that mitigates both clock and data duty cycle distortion for the transmitted data.

Abstract: In some embodiments, an antenna module includes an antenna element having a first side and a second side opposite the first side; a spacer structure disposed at the second side of the antenna element and configured to define a cavity, the spacer structure configured to be physically and electrically couplable with a printed circuit board (PCB) of a receiver or a transmitter; and an amplifier located within the cavity. The first side comprises a radiating side of the antenna element.

Abstract: The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is 10 configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

Abstract: In some embodiments, an antenna module includes an antenna element having a first side and a second side opposite the first side; a spacer structure disposed at the second side of the antenna element and configured to define a cavity, the spacer structure configured to be physically and electrically couplable with a printed circuit board (PCB) of a receiver or a transmitter; and an amplifier located within the cavity. The first side comprises a radiating side of the antenna element.

Abstract: An integrated circuit having a transmitter is provided. The transmitter may include a serializer, a driver, and an associated calibration circuit. The calibration circuit may include a detector and a control circuit. The control circuit may output a first control signal for selectively configuring the serializer to inject test data and may also output a second control signal for selectively inverting the input polarity of the detector. The control circuit may configure the transmitter in at least four different modes by adjusting the first and second control signals. In each of the four modes, the control circuit may sweep a clock duty cycle correction (DCC) setting that controls only the serializer until the detector flips. Codes generated in this way may be used to compute calibrated settings that mitigates both clock and data duty cycle distortion for the transmitted data.

Abstract: A computer-implemented method includes receiving a first circuit design for an integrated circuit device, determining when multiple power-drawing events are to occur at substantially the same time via one or more circuitry components of the integrated circuit device, which would have a disruptive effect on a power distribution network of the integrated circuit device, based on the first circuit design, and generating logic that schedules the more than one event so that the more than one event do not occur simultaneously. The logic is included in an event sequencer. The method also includes inserting the event sequencer into the first circuit design during compilation to create a second circuit design and outputting the second circuit design to be implemented on the integrated circuit device.

Abstract: The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is 10 configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

Abstract: The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

Abstract: A computer-implemented method includes receiving a first circuit design for an integrated circuit device, determining when multiple power-drawing events are to occur at substantially the same time via one or more circuitry components of the integrated circuit device, which would have a disruptive effect on a power distribution network of the integrated circuit device, based on the first circuit design, and generating logic that schedules the more than one event so that the more than one event do not occur simultaneously. The logic is included in an event sequencer. The method also includes inserting the event sequencer into the first circuit design during compilation to create a second circuit design and outputting the second circuit design to be implemented on the integrated circuit device.

Abstract: Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to determine whether a size of the eye opening needs to be changed. When it is determined that the size of the eye opening needs to be changed, the adaptation circuitry is operable to generate a digital signal to change a gain setting of the receiver. When the signal at the receiver's output is under-equalized, the AC gain of the receiver is increased. When the signal at the receiver's output is over-equalized, the AC gain of the receiver is decreased.