Patents by Inventor Tristan TRONIC
Tristan TRONIC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120415Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.Type: ApplicationFiled: October 1, 2022Publication date: April 11, 2024Applicant: Intel CorporationInventors: Scott B. Clendenning, Sudarat Lee, Kevin P. O'Brien, Rachel A. Steinhardt, John J. Plombon, Arnab Sen Gupta, Charles C. Mokhtarzadeh, Gauri Auluck, Tristan A. Tronic, Brandon Holybee, Matthew V. Metz, Dmitri Evgenievich Nikonov, Ian Alexander Young
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Publication number: 20240113212Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon FET. In another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. The interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Hai Li, Arnab Sen Gupta, Gauri Auluck, I-Cheng Tung, Brandon Holybee, Rachel A. Steinhardt, Punyashloka Debashis
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Publication number: 20240114696Abstract: Multiple-ferroelectric capacitor structures in memory devices, including in integrated circuit devices, and techniques for forming the structures. Insulators separating individual outer plates in a ferroelectric capacitor array are supported between wider portions of a shared, inner plate. Wider portions of an inner plate may be formed in lateral recesses between insulating layers. Ferroelectric material may be deposited over the inner plate between insulating layers after removing sacrificial layers. An etch-stop layer may protect the inner plate when sacrificial layers are removed. An etch-stop or interface layer may remain over the inner plate adjacent insulators.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Christopher Neumann, Cory Weinstein, Nazila Haratipour, Brian Doyle, Sou-Chi Chang, Tristan Tronic, Shriram Shivaraman, Uygar Avci
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Publication number: 20240105810Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Rachel A. Steinhardt, Ian Alexander Young, Dmitri Evgenievich Nikonov, Marko Radosavljevic, Matthew V. Metz, John J. Plombon, Raseong Kim, Kevin P. O'Brien, Scott B. Clendenning, Tristan A. Tronic, Dominique A. Adams, Carly Rogan, Arnab Sen Gupta, Brandon Holybee, Punyashloka Debashis, I-Cheng Tung, Gauri Auluck
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Publication number: 20240105822Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and theType: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Kevin P. O'Brien, Brandon Holybee, Carly Rogan, Dmitri Evgenievich Nikonov, Punyashloka Debashis, Rachel A. Steinhardt, Tristan A. Tronic, Ian Alexander Young, Marko Radosavljevic, John J. Plombon
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Publication number: 20240105588Abstract: An IC device includes a multilayer metal line that is at least partially surrounded by one or more electrical insulators. The multilayer metal line may be formed by stacking four layers on top of one another. The four layers may include a first layer between a second layer and a third layer. The first layer may include Al. The second or third layer may include W. The fourth layer may be a conductive or dielectric layer. The second layer, third layer, and fourth layer can protect the first layer from defects in Al core layer during fabrication or operation of the multilayer metal line. Substrative etch may be performed on the stack of the four layers to form openings. An electrical insulator may be deposited into to the openings to form multiple metal lines that are separated by the electrical insulator. A via may be formed over the third layer.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Applicant: Intel CorporationInventors: Ilya V. Karpov, Shafaat Ahmed, Matthew V. Metz, Darren Anthony Denardis, Nafees Aminul Kabir, Tristan A. Tronic
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Publication number: 20240097031Abstract: In one embodiment, a transistor device includes a gate material layer on a substrate, a ferroelectric (FE) material layer on the gate material, a semiconductor channel material layer on the FE material layer, a first source/drain material on the FE material layer and adjacent the semiconductor channel material layer, and a second source/drain material on the FE material layer and adjacent the semiconductor channel material layer and on an opposite side of the semiconductor channel material layer from the first source/drain material. A first portion of the FE material layer is directly between the gate material and the first source/drain material, and a second portion of the FE material layer is directly between the gate material and the second source/drain material.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Applicant: Intel CorporationInventors: Punyashloka Debashis, Rachel A. Steinhardt, Brandon Holybee, Kevin P. O'Brien, Dmitri Evgenievich Nikonov, John J. Plombon, Ian Alexander Young, Raseong Kim, Carly Rogan, Dominique A. Adams, Arnab Sen Gupta, Marko Radosavljevic, Scott B. Clendenning, Gauri Auluck, Hai Li, Matthew V. Metz, Tristan A. Tronic, I-Cheng Tung
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Publication number: 20240063071Abstract: Multi-die composite structures including a multi-layered inorganic dielectric gap fill material within a space between adjacent IC dies. A first layer of fill material with an inorganic composition may be deposited over IC dies with a high-rate deposition process, for example to at least partially fill a space between the IC dies. The first layer of fill material may then be partially removed to modify a sidewall slope of the first layer or otherwise reduce an aspect ratio of the space between the IC dies. Another layer of fill material may be deposited over the lower layer of fill material, for example with the same high-rate deposition process. This dep-etch-dep cycle may be repeated any number of times to backfill spaces between IC dies. The multi-layer fill material may then be globally planarized and the IC die package completed and/or assembled into a next-level of integration.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Jeffery Bielefeld, Adel Elsherbini, Bhaskar Jyoti Krishnatreya, Feras Eid, Gauri Auluck, Kimin Jun, Mohammad Enamul Kabir, Nagatoshi Tsunoda, Renata Camillo-Castillo, Tristan A. Tronic, Xavier Brun
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Publication number: 20240047543Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.Type: ApplicationFiled: October 20, 2023Publication date: February 8, 2024Inventors: Rami HOURANI, Richard VREELAND, Giselle ELBAZ, Manish CHANDHOK, Richard E. SCHENKER, Gurpreet SINGH, Florian GSTREIN, Nafees KABIR, Tristan A. TRONIC, Eungnak HAN
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INTERCONNECTS HAVING A PORTION WITHOUT A LINER MATERIAL AND RELATED STRUCTURES, DEVICES, AND METHODS
Publication number: 20240038661Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.Type: ApplicationFiled: October 16, 2023Publication date: February 1, 2024Applicant: Intel CorporationInventors: Manish CHANDHOK, Richard SCHENKER, Tristan TRONIC -
Patent number: 11869894Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.Type: GrantFiled: July 13, 2022Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
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Publication number: 20230420364Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the device and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. The second transistors are part of a voltage regulation architecture to regulate voltage supply to the die.Type: ApplicationFiled: June 24, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Kevin P. O'Brien, Tristan A. Tronic, Ande Kitamura, Ashish Verma Penumatcha, Carl Hugo Naylor, Chelsey Dorow, Kirby Maxey, Scott B. Clendenning, Sudarat Lee, Uygar E. Avci
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Publication number: 20230402499Abstract: Capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such capacitors include a transition metal oxide dielectric between two electrodes, at least one of which includes a conductive metal oxide layer on the transition metal oxide dielectric and a high density metal layer on the conductive metal oxide.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Applicant: Intel CorporationInventors: Thomas Sounart, Kaan Oguz, Neelam Prabhu Gaunkar, Tristan Tronic
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Interconnects having a portion without a liner material and related structures, devices, and methods
Patent number: 11837542Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.Type: GrantFiled: January 24, 2022Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Manish Chandhok, Richard Schenker, Tristan Tronic -
Patent number: 11837644Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.Type: GrantFiled: September 23, 2019Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Rami Hourani, Richard Vreeland, Giselle Elbaz, Manish Chandhok, Richard E. Schenker, Gurpreet Singh, Florian Gstrein, Nafees Kabir, Tristan A. Tronic, Eungnak Han
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Publication number: 20230352598Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).Type: ApplicationFiled: June 30, 2023Publication date: November 2, 2023Applicant: Intel CorporationInventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
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Patent number: 11769814Abstract: A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask.Type: GrantFiled: June 27, 2019Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Kevin L. Lin, Tristan Tronic
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Patent number: 11764306Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.Type: GrantFiled: September 13, 2021Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
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Patent number: 11742429Abstract: Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance.Type: GrantFiled: October 22, 2021Date of Patent: August 29, 2023Assignee: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Li Huey Tan, Tristan A. Tronic, Benjamin Chu-Kung, Jack T. Kavalieros, Tahir Ghani
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Publication number: 20230113614Abstract: Thin film transistors having CMOS functionality integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first device including a first two-dimensional (2D) material layer, and a first gate stack around the first 2D material layer. The first gate stack has a gate electrode around a gate dielectric layer. A second device is stacked on the first device. The second device includes a second 2D material layer, and a second gate stack around the second 2D material layer. The second gate stack has a gate electrode around a gate dielectric layer. The second 2D material layer has a composition different than a composition of the first 2D material layer.Type: ApplicationFiled: September 24, 2021Publication date: April 13, 2023Inventors: Kevin P. O'BRIEN, Chelsey DOROW, Carl NAYLOR, Kirby MAXEY, Sudarat LEE, Ashish Verma PENUMATCHA, Uygar E. AVCI, Scott B. CLENDENNING, Urusa ALAAN, Tristan A. TRONIC