Patents by Inventor Tristan Y. Ma
Tristan Y. Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942361Abstract: Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.Type: GrantFiled: June 15, 2021Date of Patent: March 26, 2024Assignee: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Patent number: 11778832Abstract: Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.Type: GrantFiled: May 3, 2021Date of Patent: October 3, 2023Assignee: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Publication number: 20220404115Abstract: Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component). In some embodiments, a method may include providing a plurality of device structures extending from a base, each of the plurality of device structures including a first sidewall opposite a second sidewall and a top surface extending between the first and second sidewalls, and providing a seed layer over the plurality of device structures. The method may further include forming a dielectric layer along just the top surface and along an upper portion of the first and second sidewalls using an angled deposition delivered to the plurality of device structures at a non-zero angle of inclination relative to a perpendicular extending from an upper surface of the base, and forming a fill material within one or more trenches defined by the plurality of device structures.Type: ApplicationFiled: August 23, 2022Publication date: December 22, 2022Applicant: Applied Materials, Inc.Inventors: M. Arif Zeeshan, Tristan Y. Ma, Kelvin Chan
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Publication number: 20220399225Abstract: Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.Type: ApplicationFiled: June 15, 2021Publication date: December 15, 2022Applicant: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Publication number: 20220352182Abstract: Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.Type: ApplicationFiled: May 3, 2021Publication date: November 3, 2022Applicant: Applied Materials, Inc.Inventors: Armin Saeedi Vahdat, Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam
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Patent number: 11459652Abstract: Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component). In some embodiments, a method may include providing a plurality of device structures extending from a base, each of the plurality of device structures including a first sidewall opposite a second sidewall and a top surface extending between the first and second sidewalls, and providing a seed layer over the plurality of device structures. The method may further include forming a dielectric layer along just the top surface and along an upper portion of the first and second sidewalls using an angled deposition delivered to the plurality of device structures at a non-zero angle of inclination relative to a perpendicular extending from an upper surface of the base, and forming a fill material within one or more trenches defined by the plurality of device structures.Type: GrantFiled: October 16, 2020Date of Patent: October 4, 2022Assignee: Applied Materials, Inc.Inventors: M. Arif Zeeshan, Tristan Y. Ma, Kelvin Chan
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Publication number: 20220119938Abstract: Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component). In some embodiments, a method may include providing a plurality of device structures extending from a base, each of the plurality of device structures including a first sidewall opposite a second sidewall and a top surface extending between the first and second sidewalls, and providing a seed layer over the plurality of device structures. The method may further include forming a dielectric layer along just the top surface and along an upper portion of the first and second sidewalls using an angled deposition delivered to the plurality of device structures at a non-zero angle of inclination relative to a perpendicular extending from an upper surface of the base, and forming a fill material within one or more trenches defined by the plurality of device structures.Type: ApplicationFiled: October 16, 2020Publication date: April 21, 2022Applicant: Applied Materials, Inc.Inventors: M. Arif Zeeshan, Tristan Y. Ma, Kelvin Chan
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Publication number: 20210189566Abstract: A ribbon beam plasma enhanced chemical vapor deposition (PECVD) system comprising a process chamber containing a platen for supporting a substrate, and a plasma source disposed adjacent the process chamber and adapted to produce free radicals in a plasma chamber, the plasma chamber having an aperture associated therewith for allowing a beam of the free radicals to exit the plasma chamber, wherein the process chamber is maintained at a first pressure and the plasma chamber is maintained at a second pressure greater than the first pressure for driving the free radicals from the plasma chamber into the process chamber.Type: ApplicationFiled: April 5, 2020Publication date: June 24, 2021Applicant: APPLIED Materials, Inc.Inventors: John Hautala, Tristan Y. MA, Peter F. Kurunczi
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Patent number: 10990014Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.Type: GrantFiled: November 22, 2019Date of Patent: April 27, 2021Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
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Patent number: 10937663Abstract: Disclosed are methods for removing bridge defects using an angled implant and selective photoresist etch. In one embodiment, a method includes providing a semiconductor device including plurality of photoresist lines on a stack of layers, wherein a bridge defect extends between two or more photoresist lines of the plurality of photoresist lines. The method may further include implanting a sidewall and an upper surface of the two or more photoresist lines with an ion beam disposed at an angle, the angle being a non-zero angle of inclination with respect to a perpendicular to a plane of the upper surface of the stack of layers. The method may further include etching the semiconductor device to remove the bridge defect.Type: GrantFiled: September 25, 2018Date of Patent: March 2, 2021Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Tristan Y. Ma, Juiyuan Hsu
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Publication number: 20200096870Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.Type: ApplicationFiled: November 22, 2019Publication date: March 26, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
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Publication number: 20200098589Abstract: Disclosed are methods for removing bridge defects using an angled implant and selective photoresist etch. In one embodiment, a method includes providing a semiconductor device including plurality of photoresist lines on a stack of layers, wherein a bridge defect extends between two or more photoresist lines of the plurality of photoresist lines. The method may further include implanting a sidewall and an upper surface of the two or more photoresist lines with an ion beam disposed at an angle, the angle being a non-zero angle of inclination with respect to a perpendicular to a plane of the upper surface of the stack of layers. The method may further include etching the semiconductor device to remove the bridge defect.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Tristan Y. MA, Juiyuan Hsu
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Patent number: 10553448Abstract: A method of processing a layer. The method may include providing the layer on a substrate, the substrate defining a substrate plane; directing an ion beam to an exposed surface of the layer in an ion exposure when the substrate is disposed in a first rotational position, the ion beam having a first ion trajectory, the first ion trajectory extending along a first direction, wherein the first ion trajectory forms a non-zero angle of incidence with respect to a perpendicular to the substrate plane; performing a rotation by rotating the substrate with respect to the ion beam about the perpendicular from the first rotational position to a second rotational position; and directing the ion beam to the exposed surface of the layer in an additional ion exposure along the first ion trajectory when the substrate is disposed in the second rotational position.Type: GrantFiled: October 31, 2016Date of Patent: February 4, 2020Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Tristan Y. Ma, Morgan Evans, Kevin Anglin, Robert J. Masci, John Hautala
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Patent number: 10545408Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.Type: GrantFiled: October 18, 2017Date of Patent: January 28, 2020Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
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Patent number: 10310379Abstract: A method for patterning a substrate, comprising: providing a photoresist patterning feature on the substrate, the substrate defining a substrate plane, the photoresist patterning feature having a softening temperature below 200° C. The method may include directing a first ion species into the photoresist patterning feature during a first exposure; and depositing a sidewall layer on the patterning feature after the directing at a deposition temperature, the deposition temperature being 200° C. or greater.Type: GrantFiled: March 14, 2017Date of Patent: June 4, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Tristan Y. Ma, Maureen K. Petterson, John Hautala, Steven R. Sherman
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Patent number: 10222202Abstract: An apparatus may include a processor and memory unit, including a control routine having a measurement processor to determine, based upon a first set of scatterometry measurements, a first change in a first dimension of a first set of substrate features along a first direction. The first set of substrate features may be elongated along a second direction perpendicular to the first direction. The measurement processor may be to determine, based upon a second set of scatterometry measurements, a second change in dimension of a second set of substrate features along the second direction, wherein the second set of substrate features is elongated along the first direction. The apparatus may include a control processor to generate an error signal when a figure of merit based upon the first change and the second change lies outside a target range.Type: GrantFiled: May 25, 2017Date of Patent: March 5, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Morgan D. Evans, Simon Ruffell, Tristan Y. Ma, Kevin Anglin
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Publication number: 20190056914Abstract: A method of patterning a substrate may include providing a blanket photoresist layer on the substrate; performing an ion implantation procedure of an implant species into the blanket photoresist layer, the implant species comprising an enhanced absorption efficiency at a wavelength in the extreme ultraviolet (EUV) range; and subsequent to the performing the ion implantation procedure, performing a patterned exposure to expose the blanket photoresist layer to EUV radiation.Type: ApplicationFiled: October 18, 2017Publication date: February 21, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Tristan Y. Ma, Huixiong Dai, Anthony Renau, John Hautala, Joseph Olson
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Publication number: 20180340769Abstract: An apparatus may include a processor and memory unit, including a control routine having a measurement processor to determine, based upon a first set of scatterometry measurements, a first change in a first dimension of a first set of substrate features along a first direction. The first set of substrate features may be elongated along a second direction perpendicular to the first direction. The measurement processor may be to determine, based upon a second set of scatterometry measurements, a second change in dimension of a second set of substrate features along the second direction, wherein the second set of substrate features is elongated along the first direction. The apparatus may include a control processor to generate an error signal when a figure of merit based upon the first change and the second change lies outside a target range.Type: ApplicationFiled: May 25, 2017Publication date: November 29, 2018Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Morgan D. Evans, Simon Ruffell, Tristan Y. MA, Kevin Anglin
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Publication number: 20180204719Abstract: A method for patterning a substrate, comprising: providing a photoresist patterning feature on the substrate, the substrate defining a substrate plane, the photoresist patterning feature having a softening temperature below 200° C. The method may include directing a first ion species into the photoresist patterning feature during a first exposure; and depositing a sidewall layer on the patterning feature after the directing at a deposition temperature, the deposition temperature being 200° C. or greater.Type: ApplicationFiled: March 14, 2017Publication date: July 19, 2018Inventors: Tristan Y. Ma, Maureen K. Petterson, John Hautala, Steven R. Sherman
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Publication number: 20180122650Abstract: A method of processing a layer. The method may include providing the layer on a substrate, the substrate defining a substrate plane; directing an ion beam to an exposed surface of the layer in an ion exposure when the substrate is disposed in a first rotational position, the ion beam having a first ion trajectory, the first ion trajectory extending along a first direction, wherein the first ion trajectory forms a non-zero angle of incidence with respect to a perpendicular to the substrate plane; performing a rotation by rotating the substrate with respect to the ion beam about the perpendicular from the first rotational position to a second rotational position; and directing the ion beam to the exposed surface of the layer in an additional ion exposure along the first ion trajectory when the substrate is disposed in the second rotational position.Type: ApplicationFiled: October 31, 2016Publication date: May 3, 2018Inventors: Tristan Y. Ma, Morgan Evans, Kevin Anglin, Robert J. Masci, John Hautala