Patents by Inventor Tristan Y. Ma

Tristan Y. Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9735013
    Abstract: Provided herein are approaches for patterning a semiconductor device. In an exemplary approach, a method includes providing a set of contact openings through a photoresist formed atop a substrate, and implanting ions into just a sidewall surface of the set of contact openings. In an exemplary approach, the ions are implanted at an implant angle nonparallel with the sidewall surface to prevent the ions from implanting a surface of the substrate within the set of contact openings, and to form a treated layer along an entire height of the contact opening. The method further includes etching the substrate within the set of contact openings after the ions are implanted into the sidewall surface. As a result, by using an angled ion implantation to the contact opening sidewall surface as a pretreatment prior to etching, local critical dimension uniformity is improved.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 15, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tristan Y. Ma, John Hautala, Maureen K. Petterson, Boya Cui
  • Publication number: 20170178911
    Abstract: Provided herein are approaches for patterning a semiconductor device. In an exemplary approach, a method includes providing a set of contact openings through a photoresist formed atop a substrate, and implanting ions into just a sidewall surface of the set of contact openings. In an exemplary approach, the ions are implanted at an implant angle nonparallel with the sidewall surface to prevent the ions from implanting a surface of the substrate within the set of contact openings, and to form a treated layer along an entire height of the contact opening. The method further includes etching the substrate within the set of contact openings after the ions are implanted into the sidewall surface. As a result, by using an angled ion implantation to the contact opening sidewall surface as a pretreatment prior to etching, local critical dimension uniformity is improved.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Inventors: Tristan Y. MA, John Hautala, Maureen K. Petterson, Boya Cui
  • Patent number: 9520290
    Abstract: Provided herein are approaches for patterning a semiconductor device. In an exemplary approach, a method includes providing a set of patterning features atop a layer of a semiconductor device, and implanting ions into a sidewall surface of the set of patterning features. The method includes implanting ions at an angle nonparallel with the sidewall surface, for example, approximately 60° to a plane normal to the sidewall surface. The method further includes etching the semiconductor device after the ions are implanted into the sidewall surface. As a result, by using an angled ion implantation as a pretreatment prior to etching, photoresist roughness is minimized, and sidewall striation and etch-induced line edge roughness is reduced. Approaches herein may also improve etch selectivity with respect to underlying layers disposed under the photoresist, as well as improved photoresist profiles.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: December 13, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tristan Y. Ma, Maureen K. Petterson
  • Patent number: 9512517
    Abstract: A method for processing a substrate may include providing a patterning feature on the substrate, the patterning feature having a sidewall. The method may further include implanting a first ion species into the patterning feature during a first exposure, the first ion species having a first implantation depth; and implanting a second ion species into the patterning feature during a second exposure, the second ion species having a second implantation depth less than the first implantation depth.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: December 6, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tristan Y. Ma, Maureen K. Petterson, John Hautala, Ludovic Godet
  • Publication number: 20160215385
    Abstract: A method for processing a substrate may include providing a patterning feature on the substrate, the patterning feature having a sidewall. The method may further include implanting a first ion species into the patterning feature during a first exposure, the first ion species having a first implantation depth; and implanting a second ion species into the patterning feature during a second exposure, the second ion species having a second implantation depth less than the first implantation depth.
    Type: Application
    Filed: March 12, 2015
    Publication date: July 28, 2016
    Inventors: Tristan Y. Ma, Maureen K. Petterson, John Hautala, Ludovic Godet