Abstract: An amplifier circuit has a variable gain amplifier including an input receiving an input signal and an open-conduction output, and an output stage including an input coupled to the open-conduction output of the variable gain amplifier and an output providing an output signal of the amplifier circuit. The variable gain amplifier has a first transistor and second transistor each having a control input receiving the input signal. A third transistor has a control terminal receiving a control signal and a first conduction terminal coupled to a first conduction terminal of the first transistor and a second conduction terminal being a first terminal of the open-conduction output. A fourth transistor has a control terminal receiving the control signal and a first conduction terminal coupled to a first conduction terminal of the second transistor and a second conduction terminal being a second terminal of the open-conduction output.

Abstract: Amplifiers with temperature-adaptive gain and peaking gain control are described. In one example, a temperature-adaptive amplifier includes an amplifier, a temperature sense circuit, and a peaking control level shifter to bias shift the output of the amplifier and adjust a peaking gain of the amplifier based on the temperature control signal. The peaking control level shifter can adjust a peaking gain of the amplifier based on the temperature control signal. The temperature-adaptive control can help to compensate for peaking gain in amplifiers based on the operating temperature of the amplifier. The control can help to compensate for unwanted changes in amplifier peaking gain, over time, resulting in more consistent peaking gain over the full operating frequency range of amplifiers.

Abstract: Aspects of temperature dependent stabilization and peaking control in amplifiers are described. An example amplifier includes a variable gain amplifier, a power amplifier, a variable compensation element coupled to the variable gain amplifier, and a controller that directs operation of the variable compensation element to adjust one or more operating characteristics of the amplifier. In one aspect, the variable compensation element comprises a variable impedance, and the controller varies the impedance across inputs of the variable gain amplifier based on temperature to stabilize the amplifier. In another aspect, the variable compensation element comprises a negative capacitance, and the controller varies a coupling of the negative capacitance across inputs of the variable gain amplifier based on temperature to linearize gain of the amplifier.

Abstract: A semiconductor device has an amplifier and common mode suppression (CMS) circuit formed on a common substrate. The CMS circuit has a first input and second input coupled for receiving an input signal and further has a first output coupled to a first input of the amplifier and a second output coupled to a second input of the amplifier to reduce common mode. The CMS circuit further has a ground plane, a first conductive trace disposed over the ground plane and coupled between the first input and first output, second conductive trace disposed over the ground plane and coupled between the second input and second output, and third conductive trace disposed over the ground plane with a first end of the third conductive trace coupled to the ground plane and a second end of the third conductive trace open circuit to form a resonator.

Abstract: This transistor sensor includes a substrate, a channel layer provided over one surface of the substrate, and a solid electrolyte layer provided between the substrate and the channel layer or over a surface of the channel layer on an opposite side to the substrate side, in which the channel layer includes an inorganic semiconductor, the solid electrolyte layer includes an inorganic solid electrolyte, and at least a portion of either one or both of the channel layer and the solid electrolyte layer includes an exposed portion exposed to outside.

Abstract: The invention to provide a system of equipment for making synthetic building materials using plastic wastes combined with industrial and agricultural scrap includes: sorting and cleaning equipment, grinding equipment, powder grinding equipment, mixing equipment, pelletizing equipment, drying equipment, hot stir equipment, shaping equipment are connected together by mechanical connectors. The database connected to the controller controls the sorting and cleaning equipment, the grinding equipment, the powder grinding equipment, the mixing equipment, the pelletizing equipment, the drying equipment, the hot stir equipment, and the shaping equipment through transmission channels. In addition, the present invention provides a method of manufacturing for making synthetic building materials using plastic wastes combined with industrial and agricultural scrap.

Abstract: The invention to provide a system of equipment for making synthetic building materials using plastic wastes combined with industrial and agricultural scrap includes: sorting and cleaning equipment, grinding equipment, powder grinding equipment, mixing equipment, pelletizing equipment, drying equipment, hot stir equipment, shaping equipment are connected together by mechanical connectors. The database connected to the controller controls the sorting and cleaning equipment, the grinding equipment, the powder grinding equipment, the mixing equipment, the pelletizing equipment, the drying equipment, the hot stir equipment, and the shaping equipment through transmission channels. In addition, the present invention provides a method of manufacturing for making synthetic building materials using plastic wastes combined with industrial and agricultural scrap.

Abstract: A thin film transistor 100 according to the invention includes a gate electrode 20, a channel 44, and a gate insulating layer 34 provided between the gate electrode 20 and the channel 44 and made of oxide (possibly containing inevitable impurities; this applies to oxide hereinafter) containing lanthanum and zirconium. The channel 44 is made of channel oxide including first oxide containing indium, zinc, and zirconium (Zr) having an atomic ratio of 0.015 or more and 0.075 or less relative to indium assumed to be 1 in atomic ratio, second oxide containing indium and zirconium (Zr) having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio, or third oxide containing indium and lanthanum having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio.

Abstract: A thin film transistor 100 according to the invention includes a gate electrode 20, a channel 44, and a gate insulating layer 34 provided between the gate electrode 20 and the channel 44 and made of oxide (possibly containing inevitable impurities; this applies to oxide hereinafter) containing lanthanum and zirconium. The channel 44 is made of channel oxide including first oxide containing indium, zinc, and zirconium (Zr) having an atomic ratio of 0.015 or more and 0.075 or less relative to indium assumed to be 1 in atomic ratio, second oxide containing indium and zirconium (Zr) having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio, or third oxide containing indium and lanthanum having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio.

Abstract: A thin film transistor 100 according to the invention includes a gate electrode 20, a channel 44, and a gate insulating layer 34 provided between the gate electrode 20 and the channel 44 and made of oxide (possibly containing inevitable impurities, this applies to oxide hereinafter) containing lanthanum and zirconium. The channel 44 is made of channel oxide including first oxide containing indium, zinc, and zirconium (Zr) having an atomic ratio of 0.015 or more and 0.075 or less relative to indium assumed to be 1 in atomic ratio, second oxide containing indium and zirconium (Zr) having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio, or third oxide containing indium and lanthanum having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio.

Abstract: A thin film transistor 100 according to the invention includes a gate electrode 20, a channel 44, and a gate insulating layer 34 provided between the gate electrode 20 and the channel 44 and made of oxide (possibly containing inevitable impurities; this applies to oxide hereinafter) containing lanthanum and zirconium. The channel 44 is made of channel oxide including first oxide containing indium, zinc, and zirconium (Zr) having an atomic ratio of 0.015 or more and 0.075 or less relative to indium assumed to be 1 in atomic ratio, second oxide containing indium and zirconium (Zr) having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio, or third oxide containing indium and lanthanum having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio.

Abstract: A thin film transistor 100 according to the invention includes a gate electrode 20, a channel 44, and a gate insulating layer 34 provided between the gate electrode 20 and the channel 44 and made of oxide (possibly containing inevitable impurities; this applies to oxide hereinafter) containing lanthanum and zirconium. The channel 44 is made of channel oxide including first oxide containing indium, zinc, and zirconium (Zr) having an atomic ratio of 0.015 or more and 0.075 or less relative to indium assumed to be 1 in atomic ratio, second oxide containing indium and zirconium (Zr) having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio, or third oxide containing indium and lanthanum having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio.