Patents by Inventor Troy A. Manning

Troy A. Manning has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11276439
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 11238920
    Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Wheeler, Troy A. Manning, Richard C. Murphy
  • Publication number: 20210407615
    Abstract: Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 30, 2021
    Inventors: Troy A. Manning, Troy D. Larsen, Jonathan D. Harms, Glen E. Hush, Timothy P. Finkbeiner
  • Publication number: 20210365268
    Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 25, 2021
    Inventors: Troy A. Manning, Jonathan D. Harms, Troy D. Larsen, Glen E. Hush, Timothy P. Finkbeiner
  • Publication number: 20210365363
    Abstract: Methods, apparatuses, and systems related to mapping a virtual address using a physical address are described. In a memory system including a memory (e.g., cache) and a content addressable memory (CAM), the CAM can be configured to search data requested by a host from the memory based on multiple indicators stored in the CAM. For example, in the event that the data stored in the memory is not searchable based on a particular indicator such as a virtual address of a memory array (e.g., main memory), the CAM be configured to search the data based on another indicator such as a physical address of the memory array. Searching the data based on multiple indicators can resolve a synonym problem.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 25, 2021
    Inventors: Harold Robert G. Trout, Glen E. Hush, Troy A. Manning, Troy D. Larsen, Timothy P. Finkbeiner
  • Publication number: 20210365188
    Abstract: The present disclosure includes systems, apparatuses and methods related to maintaining data in a sorted order in a memory array to improve access time to data in the memory array and directing access to a row of data in cache based upon an address associated with the data. In a number of embodiments, data stored in tables in sorted order can allow access to data based on upon the keys and/or the sorted order of the data, which can increase access times to data the memory array.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 25, 2021
    Inventors: Harold Robert G. Trout, Glen E. Hush, Troy A. Manning, Timothy P. Finkbeiner, Troy D. Larsen
  • Publication number: 20210365383
    Abstract: Apparatuses, systems, and methods for mapping a virtual address using a CAM are described. A parallel structure of a CAM can enable functions of a MMU to be integrated into a single operation performed using the CAM such that a virtual address of a memory array can be mapped directly to a row of a memory. An example method includes receiving an access command and address information for a memory array; identifying a virtual address and a physical address of the memory array based on the received address information; comparing, during a time period associated with the access command, the virtual address and the physical address to virtual addresses and physical addresses, respectively, of the memory array stored in a CAM; and accessing, during the time period, a row of the memory array coupled to a row of the CAM storing the virtual address and the physical address.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 25, 2021
    Inventors: Harold Robert G. Trout, Timothy P. Finkbeiner, Troy A. Manning, Glen E. Hush, Troy D. Larsen
  • Publication number: 20210365360
    Abstract: Methods, apparatuses, and systems related to mapping a virtual address using a content addressable memory (CAM) are described. In a memory system including a memory and a content addressable memory (CAM), a select line of the CAM can be coupled to a corresponding select line of the memory, which allows the memory system to map a virtual address of a memory device directly to the corresponding select line of the memory. An example method can include receiving, from a host at a memory device comprising a memory array and a content addressable memory (CAM), a first virtual address to be searched among virtual addresses stored within the CAM, identifying, in response to receipt of the first virtual address, a select line of a plurality of select lines of the CAM associated with a second virtual address matching the first virtual address, and activating, in response to identifying the select line of the CAM, a corresponding select line of the memory coupled to the identified select line of the CAM.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 25, 2021
    Inventors: Harold Robert G. Trout, Troy D. Larsen, Timothy P. Finkbeiner, Glen E. Hush, Troy A. Manning
  • Publication number: 20210365204
    Abstract: The present disclosure includes systems, apparatuses and methods related to maintaining data in a sorted order in a memory array to improve access time to data in the memory array and directing access to a row of data in cache based upon an address associated with the data. In a number of embodiments, data can be sorted by receiving a portion of data for storage in a memory device, extracting a key associated with the portion of data, determining a row of an index table to store the key, and placing the key along with a number of keys in the row of the index table in a sorted order, wherein the sorted order is in relation to keys associated with portions of data previously stored in the memory device.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 25, 2021
    Inventors: Harold Robert G. Trout, Troy D. Larsen, Troy A. Manning, Timothy P. Finkbeiner, Glen E. Hush
  • Publication number: 20210365205
    Abstract: The present disclosure includes systems, apparatuses and methods related to maintaining data in a sorted order in a memory array to improve access time to data in the memory array and directing access to a row of data in cache based upon an address associated with the data. In a number of embodiments, a number of keys that are stored in a first row of an index table can be split between the first row and a second row in response to the first row being full, where the number of keys are copied to the second row and a first portion of the number of keys remain in the first row and a second portion of the number of keys are moved to the second row.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 25, 2021
    Inventors: Harold Robert G. Trout, Troy D. Larsen, Timothy P. Finkbeiner, Troy A. Manning, Glen E. Hush
  • Publication number: 20210191624
    Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Jason T. Zawodny, Glen E. Hush, Troy A. Manning, Timothy P. Finkbeiner
  • Publication number: 20210142843
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.
    Type: Application
    Filed: October 5, 2020
    Publication date: May 13, 2021
    Inventor: Troy A. Manning
  • Publication number: 20210118478
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventor: Troy A. Manning
  • Patent number: 10942652
    Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to pre-resolved instructions. An example apparatus comprises a memory device coupled to a host via a data bus and a control bus. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes sense amplifiers and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of address translated instructions and/or constant data from the host. The memory controller is configured to write the address translated instructions and/or constant data to a plurality of locations in a bank of the memory device in parallel.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jason T. Zawodny, Glen E. Hush, Troy A. Manning, Timothy P. Finkbeiner
  • Publication number: 20210065778
    Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Inventors: Kyle B. Wheeler, Troy A. Manning, Richard C. Murphy
  • Publication number: 20210020207
    Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.
    Type: Application
    Filed: October 5, 2020
    Publication date: January 21, 2021
    Inventors: Perry V. Lea, Troy A. Manning
  • Publication number: 20210004237
    Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Kyle B. Wheeler, Richard C. Murphy, Troy A. Manning, Dean A. Klein
  • Patent number: 10878863
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 10839892
    Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kyle B. Wheeler, Troy A. Manning, Richard C. Murphy
  • Patent number: 10839867
    Abstract: The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting, using sensing circuitry, a number of data values stored in a respective number of memory cells coupled to a sense line of an array by determining a parity value corresponding to the number of data values without transferring data from the array via an input/output line. The parity value can be determined by a number of XOR operations, for instance. The method can include storing the parity value in another memory cell coupled to the sense line.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Richard C. Murphy