Patents by Inventor Troy J. Beukema
Troy J. Beukema has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10681802Abstract: P and N termination networks couple a P line and an N line to corresponding receiver inputs. Each termination network includes an electrostatic discharge protection T-coil having an input port coupled to the corresponding line, a terminal port, and a center tap port. At least one of the termination networks further includes at least one delay T-coil having a terminal port, a center tap port, and an input port coupled to the terminal port of a corresponding one of the electrostatic discharge protection T-coils. In a no delay mode, a multiplexer selectively connects the P and N electrostatic discharge protection T-coil center tap ports to the P and N inputs of the receiver. In a delay mode, the multiplexer selectively connects the delay T-coil center tap port to a corresponding one of the P input of the receiver and the N input of the receiver.Type: GrantFiled: September 4, 2019Date of Patent: June 9, 2020Assignee: International Business Machines CorporationInventors: Troy J. Beukema, Jonathan E. Proesel
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Patent number: 9853839Abstract: Various embodiments of the present invention solve the problem of generating intermediate-time information useable to drive ZFE adaptation (for example, in connection with a digital receiver). Further, various embodiments of the present invention increase flexibility by enabling user-specified over-peaking and/or under-peaking (i.e. configurable equalizer tuning) with respect to a ZFE convergence (or lock) criterion.Type: GrantFiled: May 25, 2016Date of Patent: December 26, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Troy J. Beukema, Matthew B. Baecher
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Publication number: 20170346662Abstract: Various embodiments of the present invention solve the problem of generating intermediate-time information useable to drive ZFE adaptation (for example, in connection with a digital receiver). Further, various embodiments of the present invention increase flexibility by enabling user-specified over-peaking and/or under-peaking (i.e. configurable equalizer tuning) with respect to a ZFE convergence (or lock) criterion.Type: ApplicationFiled: May 25, 2016Publication date: November 30, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Troy J. BEUKEMA, Matthew B. BAECHER
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Patent number: 9762423Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.Type: GrantFiled: December 12, 2016Date of Patent: September 12, 2017Assignee: International Business Machines CorporationInventors: Matthew B. Baecher, Troy J. Beukema, Lamiaa Msalka
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Patent number: 9755863Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.Type: GrantFiled: November 14, 2016Date of Patent: September 5, 2017Assignee: International Business Machines CorporationInventors: Matthew B. Baecher, Troy J. Beukema, Lamiaa Msalka
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Patent number: 9735988Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.Type: GrantFiled: December 12, 2016Date of Patent: August 15, 2017Assignee: International Business Machines CorporationInventors: Matthew B. Baecher, Troy J. Beukema, Lamiaa Msalka
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Patent number: 9712347Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.Type: GrantFiled: December 12, 2016Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Matthew B. Baecher, Troy J. Beukema, Lamiaa Msalka
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Patent number: 9705717Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.Type: GrantFiled: December 12, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Matthew B. Baecher, Troy J. Beukema, Lamiaa Msalka
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Publication number: 20170170996Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to a 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.Type: ApplicationFiled: December 12, 2016Publication date: June 15, 2017Inventors: Matthew B. Baecher, Troy J. Beukema, Lamiaa Msalka
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Publication number: 20170170994Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.Type: ApplicationFiled: November 14, 2016Publication date: June 15, 2017Inventors: Matthew B. Baecher, Troy J. Beukema, Lamiaa Msalka
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Publication number: 20170170995Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.Type: ApplicationFiled: December 12, 2016Publication date: June 15, 2017Inventors: Matthew B. Baecher, Troy J. Beukema, Lamiaa Msalka
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Publication number: 20170171006Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.Type: ApplicationFiled: December 12, 2016Publication date: June 15, 2017Inventors: Matthew B. Baecher, Troy J. Beukema, Lamiaa Msalka
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Publication number: 20170171005Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.Type: ApplicationFiled: December 12, 2016Publication date: June 15, 2017Inventors: Matthew B. Baecher, Troy J. Beukema, Lamiaa Msalka
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Patent number: 9584345Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.Type: GrantFiled: December 9, 2015Date of Patent: February 28, 2017Assignee: International Business Machines CorporationInventors: Matthew B. Baecher, Troy J. Beukema, Lamiaa Msalka
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Patent number: 9253004Abstract: An apparatus and method to control signal phase in a radio device includes an analog phase rotator that accepts differential in-phase (I) and quadrature (Q) inputs, connected in two differential pairs. The analog phase rotator is driven by a local oscillator and is configured to control a phase of the local oscillator's output. A phase error determination module is configured to determine phase error information based on received I and Q (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator.Type: GrantFiled: April 2, 2015Date of Patent: February 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Troy J. Beukema, Brian A. Floyd, Scott K. Reynolds, Sergey V. Rylov
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Publication number: 20150215144Abstract: An apparatus and method to control signal phase in a radio device includes an analog phase rotator that accepts differential in-phase (I) and quadrature (Q) inputs, connected in two differential pairs. The analog phase rotator is driven by a local oscillator and is configured to control a phase of the local oscillator's output. A phase error determination module is configured to determine phase error information based on received I and Q (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator.Type: ApplicationFiled: April 2, 2015Publication date: July 30, 2015Inventors: TROY J. BEUKEMA, BRIAN A. FLOYD, SCOTT K. REYNOLDS, SERGEY V. RYLOV
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Patent number: 8964825Abstract: Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current integrating amplifier circuit comprising an adjustable circuit element to tune a peaking response of the current integrator circuit, and a peaking control circuit to generate a control signal to adjust a value of the adjustable circuit element as a function of an operating condition of the current integrator circuit. The operating condition may be a specified data rate or a communication channel characteristic or both. The adjustable circuit element may be a degeneration capacitor or a bias current source.Type: GrantFiled: February 17, 2012Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Troy J. Beukema, John F. Bulzacchelli
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Patent number: 8867668Abstract: A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier.Type: GrantFiled: November 8, 2013Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Troy J. Beukema, Gautam Gangasani, Thomas H. Toifl
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Publication number: 20140133604Abstract: A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier.Type: ApplicationFiled: November 8, 2013Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Troy J. Beukema, Gautam Gangasani, Thomas H. Toifl
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Patent number: 8634787Abstract: Provision of gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (>30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components.Type: GrantFiled: August 20, 2012Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Troy J. Beukema, Scott K. Reynolds