Patents by Inventor Trung (Tim) Trinh

Trung (Tim) Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10955417
    Abstract: Described herein are methods, compositions and articles of manufacture involving neutral conjugated polymers including methods for synthesis of neutral conjugated water-soluble polymers with linkers along the polymer main chain structure and terminal end capping units. Such polymers may serve in the fabrication of novel optoelectronic devices and in the development of highly efficient biosensors. The invention further relates to the application of these polymers in assay methods.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: March 23, 2021
    Assignee: SIRIGEN II LIMITED
    Inventors: Brent S. Gaylord, Glenn P. Bartholomew, Russell A. Baldocchi, Janice W. Hong, William H. Huisman, Yongchao Liang, Trung Nguyen, Lan T. Tran, Jean M. Wheeler, Adrian Charles Vernon Palmer, Frank Peter Uckert
  • Patent number: 10956148
    Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary W. Batchelor, Veronica S. Davila, Enrique Q. Garcia, Robin Han, Jay T. Kirch, Ronald D. Martens, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
  • Patent number: 10956354
    Abstract: Provided are techniques for detecting a type of storage adapter connected to an Input/Output (I/O) bay and miscabling of a microbay housing the storage adapter. Under control of an Input/Ouput (I/O) bay, cable sidebands are driven high for a predetermined period of time. It is determined whether a cable sidebands response has been detected that indicates that the cable sidebands have been driven low. In response to determining that the cable sidebands response has been detected, it is determined that the I/O bay is connected to a first storage adapter supporting a first protocol for the cable sidebands. In response to determining that the cable sidebands response has not been detected, it is determined that the I/O bay is connected to a second storage adapter supporting a second protocol for the cable sidebands. Moreover, I/O bay and port numbers stored by the microbay are used to determine miscabling.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Gary W. Batchelor, Enrique Q. Garcia, Jay T. Kirch, Trung N. Nguyen, Todd C Sorenson
  • Publication number: 20210081503
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer-readable media that can determine an answer to a query based on matching probabilities for combinations of respective candidate answers. For example, the disclosed systems can utilize a gated-self attention mechanism (GSAM) to interpret inputs that include contextual information, a query, and candidate answers. The disclosed systems can also utilize a memory network in tandem with the GSAM to form a gated self-attention memory network (GSAMN) to refine outputs or predictions over multiple reasoning hops. Further, the disclosed systems can utilize transfer learning of the GSAM/GSAMN from an initial training dataset to a target training dataset.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 18, 2021
    Inventors: Quan Tran, Tuan Manh Lai, Trung Bui
  • Patent number: 10949277
    Abstract: Provided are a computer program product for managing bus interface errors in a storage system coupled to a host and storage. A determination is made as to whether a first number of correctable errors on a first bus interface, connecting a first processing unit to the storage, exceeds a second number of correctable errors on a second bus interface, connecting a second processing unit to the storage, by a difference threshold. The correctable errors in the first and second bus interfaces are detected and corrected in the first and second bus interfaces by first hardware and second hardware, respectively. In response to determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, at least a portion of Input/Output (I/O) requests are redirected to a second processing unit using the second bus interface to connect to the storage.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 10950834
    Abstract: A battery packaging arrangement. The battery packaging arrangement includes a first base configured to be fixedly coupled to a frame of a vehicle, a second base moveable with respect to the first base, and a plurality of cooling columns inter-disposed between the first base and the second base. Each of the plurality of cooling columns includes a plurality of receiving surfaces for receiving a corresponding plurality of battery cells. Each of the plurality of cooling columns is further configured to deform when the second base in response to a force moves towards the first base.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: March 16, 2021
    Assignee: Purdue Research Foundation
    Inventors: Hangjie Liao, Waterloo Tsutsui, Trung N Nguyen, Thomas Heinrich Siegmund, Weinong Wayne Chen
  • Publication number: 20210073050
    Abstract: A method is disclosed to reduce lock contention in a data storage system. The method dispatches, on a first processor core, a task configured to acquire a lock on a data storage resource, such as memory. The method then determines whether the first processor core is associated with the data storage resource. If the first processor core is not associated with the data storage resource, the method re-dispatches the task on a second processor core that is associated with the data storage resource. In certain embodiments, the task is only re-dispatched on the second processor core if an amount of effort required to acquire the lock is above a selected threshold. If, on the other hand, the first processor core is associated with the data storage resource, the method executes the task on the first processor core. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Applicant: International Business Machines Corporation
    Inventors: Clint A. Hardy, Lokesh M. Gupta, Trung N. Nguyen, Seamus Burke
  • Publication number: 20210073090
    Abstract: A first non-volatile dual in-line memory module (NVDIMM) of a first server and a second NVDIMM of a second server are armed during initial program load in a dual-server based storage system to configure the first NVDIMM and the second NVDIMM to retain data on power loss. Prior to initiating a safe data commit scan to destage modified data from the first server to a secondary storage, a determination is made as to whether the first NVDIMM is armed. In response to determining that the first NVDIMM is not armed, a failover is initiated to the second server.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Inventors: Matthew G. Borlick, Sean Patrick Riley, Brian Anthony Rinaldi, Trung N. Nguyen, Lokesh M. Gupta
  • Publication number: 20210064205
    Abstract: A controller for controlling the display of secondary digital content displayed in an overlay above a primary video stream. The controller includes a touch interface device, a processor, and a memory storing non-transitory instructions. These instructions, when executed, can include (i) detecting a first input gesture by a user on the touch interface device, (ii) in response to detecting the first input gesture, selecting an application for display, (iii) detecting a second input gesture by the user on the touch interface device, (iv) in response to detecting the second input gesture, scrolling through a currently-displayed layer of the selected application displayed, (v) detecting a third input gesture by the user on the touch interface device, and (vi) in response to detecting the third input gesture, scrolling between layers of the selected application in a simulated Z-space.
    Type: Application
    Filed: September 14, 2020
    Publication date: March 4, 2021
    Inventors: Dale Alan HERIGSTAD, Nam Hoai DO, Nhan Minh DANG, Hieu Trung TRAN, Quang Sy DINH, Thang Viet NGUYEN, Long Hai NGUYEN, Linh Chi NGUYEN
  • Publication number: 20210066547
    Abstract: A semiconductor component for fabricating semiconductor structures includes a plate having an elastomeric polymer layer thereon and at least one semiconductor structure adhesively attached to the elastomeric polymer layer. A semiconductor structure includes a first semiconductor layer and a second semiconductor layer with an active layer therebetween. The semiconductor structure also includes a plurality of mesas including at least one shorting mesa and at least one non-shorting mesa physically connected to the first semiconductor layer. A method for fabricating semiconductor structures includes the steps of: forming a plurality of semiconductor layer structures on the substrate, forming an elastomeric polymer layer on a receiving plate and attaching the elastomeric polymer layer to the semiconductor structures, and separating the semiconductor structures from the substrate with the semiconductor structures attached to the receiving plate.
    Type: Application
    Filed: July 23, 2020
    Publication date: March 4, 2021
    Applicant: TSLC CORPORATION
    Inventors: Trung Tri Doan, CHEN-FU CHU, SHIH-KAI CHAN, DAVID TRUNG DOAN, YI-FENG SHIH
  • Publication number: 20210066541
    Abstract: A method for fabricating light emitting diode (LED) dice includes the steps of: providing a substrate, and forming a plurality of die sized semiconductor structures on the substrate. The method also includes the steps of providing a receiving plate having an elastomeric polymer layer, placing the substrate and the receiving plate in physical contact with an adhesive force applied by the elastomeric polymer layer, and performing a laser lift-off (LLO) process by directing a uniform laser beam through the substrate to the semiconductor layer at an interface with the substrate to lift off the semiconductor structures onto the elastomeric polymer layer. During the laser lift-off (LLO) process the elastomeric polymer layer functions as a shock absorber to reduce momentum transfer, and as an adhesive surface to hold the semiconductor structures in place on the receiving plate.
    Type: Application
    Filed: August 7, 2020
    Publication date: March 4, 2021
    Applicants: SemiLEDs Corporation, SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Chen-Fu Chu, Shih-Kai CHAN, Yi-Feng SHIH, David Trung DOAN, Trung Tri DOAN, Yoshinori OGAWA, Kohei OTAKE, Kazunori KONDO, Keiji OHORI, Taichi KITAGAWA, Nobuaki MATSUMOTO, Toshiyuki OZAI, Shuhei UEDA
  • Publication number: 20210063651
    Abstract: A method is disclosed to identify a port that is associated with a faulty cable. In one embodiment, such a method identifies a cable to replace. The cable provides a path between a first port, residing on a first component, and a second port, residing on a second component. The method further identifies whether an alternative path, bypassing the first cable, exists between the first component and the second component. In the event the alternative path exists, the method sends, over the alternative path, from the first component to the second component, a command to activate an indicator on the second port. This command is received and executed by the second component to activate the indicator. A corresponding apparatus and computer program product are also disclosed.
    Type: Application
    Filed: September 2, 2019
    Publication date: March 4, 2021
    Applicant: International Business Machines Corporation
    Inventors: Todd C. Sorenson, Gary W. Batchelor, Ya-Huey Juan, Seamus Burke, Maoyun Tang, Trung N. Nguyen
  • Patent number: 10936369
    Abstract: In a computing storage environment having multiple processor devices, lists of Task Control Blocks (TCBs) are maintained in a processor-specific manner, such that each of the multiple processor devices is assigned a local TCB list. The local TCB list of each of the multiple processor devices is populated with a respective number of TCBs from a global TCB list. The local TCB list of each of the multiple processor devices exchanges TCBs with the global TCB list during processes to maintain the local TCB list of each of the multiple processor devices at the respective number.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Trung N. Nguyen, Sean P. Riley
  • Patent number: 10936003
    Abstract: Systems and methods are disclosed for phase locking multiple clocks of different frequencies. In certain embodiments, an apparatus may be configured to downsample a first clock having a first frequency and a second clock having a second frequency into downsampled clocks having the same frequency. The apparatus may adjust a frequency of the second clock so that the downsampled clocks are phase aligned. The apparatus may reset counters of the divider circuits that perform the downsampling so align them to a counter for the first clock. A counter for the second clock may also be reset to align with the counter for the first clock. The synchronized clocks may be applied in data storage operations, such as self-servo writing operations, where the first clock may be a read clock and the second clock may be a write clock.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 2, 2021
    Assignee: Seagate Technology LLC
    Inventors: Zheng Wu, Jason Bellorado, Marcus Marrow, Trung Thuc Nguyen, Wing Fai Hui, Kin Ming Chan
  • Publication number: 20210056448
    Abstract: A computer-implemented method for computing inconsistency explanations in a first data set, enhanced with an ontology, the first data set comprising data elements, called individuals, and facts about the individuals; the facts are expressed according to an ontology language in terms of class assertions and/or property assertions, a class assertion relates one individual with a class and a property assertion relates one individual with a second individual. The ontology includes a formal explicit description of the classes and/or properties and further including axioms about the classes and/or properties; wherein the method includes the steps of: constructing a second data set being an abstract description of the first data set; computing inconsistency explanations in the second data set with regard to the axioms of the ontology, and computing inconsistency explanations for the first data set with regard to the ontology based on the computed inconsistency explanations in the second data set.
    Type: Application
    Filed: July 20, 2020
    Publication date: February 25, 2021
    Inventors: Daria Stepanova, Evgeny Kharlamov, Jannik Stroetgen, Mohamed Gad-Elrab, Trung Kien Tran
  • Publication number: 20210057718
    Abstract: The present disclosure provides an electrode structure including a metal thin film and a patterned graphene-graphitic carbon composite layer disposed on the metal thin film, a method for fabricating the electrode structure using laser printing, and an electrochemical device including the same.
    Type: Application
    Filed: June 1, 2018
    Publication date: February 25, 2021
    Inventors: Byung Hee HONG, Sang Min KANG, Quang Trung TRUONG
  • Publication number: 20210058345
    Abstract: The present disclosure relates to utilizing a graph neural network to accurately and flexibly identify text phrases that are relevant for responding to a query. For example, the disclosed systems can generate a graph topology having a plurality of nodes that correspond to a plurality of text phrases and a query. The disclosed systems can then utilize a graph neural network to analyze the graph topology, iteratively propagating and updating node representations corresponding to the plurality of nodes, in order to identify text phrases that can be used to respond to the query. In some embodiments, the disclosed systems can then generate a digital response to the query based on the identified text phrases.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Seunghyun Yoon, Franck Dernoncourt, Doo Soon Kim, Trung Bui
  • Patent number: 10928414
    Abstract: A method for determining a flow speed of a liquid in a fluid conduit is provided. During a signal-generating phase, an impulse signal is applied to a first ultrasonic transducer. A response signal is then received at a second ultrasonic transducer. A measuring signal is later derived from the response signal, wherein the derivation comprises reversing a signal portion with respect to time. During a measurement phase, a liquid moves with respect to the fluid conduit. The measuring signal is then applied to one of the two transducers and a response signal of the measuring signal is measured at the other transducer. A flow speed is derived from the response signal of the measuring signal.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: February 23, 2021
    Assignee: GWF MessSysteme AG
    Inventors: Thomas Werner Hies, Trung Dung Luong, Claus-Dieter Ohl, Juergen Heinz-Friedrich Skripalle
  • Publication number: 20210050033
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media for determining speech emotion. In particular, a speech emotion recognition system generates an audio feature vector and a textual feature vector for a sequence of words. Further, the speech emotion recognition system utilizes a neural attention mechanism that intelligently blends together the audio feature vector and the textual feature vector to generate attention output. Using the attention output, which includes consideration of both audio and text modalities for speech corresponding to the sequence of words, the speech emotion recognition system can apply attention methods to one of the feature vectors to generate a hidden feature vector. Based on the hidden feature vector, the speech emotion recognition system can generate a speech emotion probability distribution of emotions among a group of candidate emotions, and then select one of the candidate emotions as corresponding to the sequence of words.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: Trung Bui, Subhadeep Dey, Seunghyun Yoon
  • Publication number: 20210050014
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media for generating dialogue responses based on received utterances utilizing an independent gate context-dependent additive recurrent neural network. For example, the disclosed systems can utilize a neural network model to generate a dialogue history vector based on received utterances and can use the dialogue history vector to generate a dialogue response. The independent gate context-dependent additive recurrent neural network can remove local context to reduce computation complexity and allow for gates at all time steps to be computed in parallel. The independent gate context-dependent additive recurrent neural network maintains the sequential nature of a recurrent neural network using the hidden vector output.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Inventors: Quan Tran, Trung Bui, Hung Bui