Abstract: A circuitboard assembly in which power carrying circuitboard traces between MOSFETs or the like and edge terminals are replaced with metal leadframe structures which also serve to perform a heat dissipation function. Each of the leadframes comprises a first planar portion which is bonded by a thermally conductive epoxy to the top surface of a MOSFET and a second elevated planar portion which extends parallel to but above the circuitboard surface into contact with an edge-mounted terminal header. The leadframes may be provided with support legs as well as additional heat dissipating fins.

Abstract: An adjustable bimetal snap disc thermostat is disclosed which provides conventional resistance-type heaters symmetrically positioned adjacent one side of the snap disc to allow adjustment of the operating temperature of the thermostat. The heaters are supported in accurate, very close proximity to the bimetal snap disc to ensure excellent heat transfer thereto. Additionally, the volume of the chamber within which the heaters are supported is reduced by a bridge portion which also serves to further reinforce the outer housing walls. Additionally, guide surfaces for the heater terminals are provided to facilitate assembly.

Abstract: The present invention relates to the production of texturized microcrystalline cellulose from raw pulp material. This texturized microcrystalline cellulose can then be used for surface treatment of paper or paper board. Additionally, the texturized microcrystalline cellulose may be used as a starting material for production of paper or paper board.

Abstract: A process for producing microcrystalline cellulose comprised of the steps of contacting a paper grade pulp with an alkali hydrolysis agent, washing the hydrolyzed pulp and contacting the hydrolyzed pulp with an acid hydrolysis agent and washing the acid hydrolyzed product.

Abstract: An adjustable bimetal snap disc thermostat is disclosed which provides conventional resistance-type heaters symmetrically positioned adjacent one side of the snap disc to allow adjustment of the operating temperature of the thermostat. The heaters are supported in accurate, very close proximity to the bimetal snap disc to ensure excellent heat transfer thereto. Additionally, the volume of the chamber within which the heaters are supported is reduced by a bridge portion which also serves to further reinforce the outer housing walls. Additionally, guide surfaces for the heater terminals are provided to facilitate assembly.

Abstract: An adjustable bimetal snap disc thermostat is disclosed which provides conventional resistance-type heaters symmetrically positioned adjacent one side of the snap disc to allow adjustment of the operating temperature of the thermostat. The heaters are supported in accurate, very close proximity to the bimetal snap disc to ensure excellent heat transfer thereto. Additionally, the volume of the chamber within which the heaters are supported is reduced by a bridge portion which also serves to further reinforce the outer housing walls. Additionally, guide surfaces for the heater terminals are provided to facilitate assembly.

Abstract: A method of testing semiconductor devices on a wafer, including a tasting circuit formed on the wafer for providing an output signal indicative of at least one operational characteristic of the devices. The output signal provided by the testing circuit is compatible for monitoring using an integrated circuit tester. The testing circuit includes an oscillator, an N-bit counter, and an N-bit shift register, all formed on the semiconductor wafer. The tester resets the counter and enables the oscillator, at which time the oscillator produces oscillator pulses at an oscillator frequency. During a predetermined time period, the counter receives and counts the oscillator pulses from the oscillator, and produces a pulse count corresponding to the number of oscillator pulses received. The shift register receives the count from the counter as an N-bit digital data word. The tester shifts the N number of bits of the digital data word out of the shift register, and manipulates the bits to determine a count value.

Abstract: A method for signal detection uses a likelihood ratio derived from the received signal to produce an estimate of a speech signal that has been corrupted by noise during transmission. The received signal is input to a receiver filter and a voice-activity detector. The receiver filter filters the received signal to produce a filter output signal. The voice-activity detector generates a likelihood ratio based on the received signal, which is then used to produce a speech-probability estimate indicating the probability that the received signal includes a speech signal. The filter output signal is combined with the speech-probability estimate output from the voice-activity detector to generate a soft estimate of the original speech signal.

Abstract: Provided is a universal decoder test board (UDTB) capable of performing the package interface and pin scrambling functions of a conventional DUT board with a variety of different package designs. The UDTB is designed such that it is capable of interfacing with a variety of different tester interface boards, each tester interface board associated with its own hardware manufacturer tester. The UDTB significantly reduces the time and expense invested in test boards required for testing semiconductor device packages for a variety of different manufacturers'platforms by allowing a given package type to be tested with a plurality of testers on the same UDTB.

Abstract: An inkjet printer includes a plastic platen and a structural member extending upward from the base of the printer. The printing surface is supported by the upper surface of the structural member. This surface is held flat to within very tight tolerances. The bottom of the platen printing surface is retained against this surface so that it conforms to the shape of this surface structural member to create a substantially flat printing surface.

Abstract: A late cancel method and apparatus for a high performance microprocessor system is disclosed. The invention is advantageously utilized in a microprocessor system comprising a processor, an external cache memory and a main memory. The processor incorporates logic to determine whether an access directed to the external cache memory has resulted in a cache hit or miss. In operation, the processor requests a desired instruction from the external cache memory which provides a cache word and cache tag to the processor before a validity determination has been made. The processor determines whether the instruction is valid, while concurrently, the processor begins to pre-decode and decode the cache word as an instruction. If the processor determines that a cache hit has occurred, the cache word proceeds normally through decoding to execution by the processor.

Abstract: A microprocessor comprised of Instruction Fetch Unit (10), Instruction Decoder (12), Pipeline Sequencer (14), Register File (16), Multiply/Divider-Unit, Execution Unit, and REG coprocessors block (18) and instruction cache, Address Generation Unit, local register cache, and MEM coprocessors block (20). The Instruction Cache provides the Instruction fetch unit (10) with instructions every cycle. The instruction sequencer (IS) includes the Fetch Unit (IFU-10), the Instruction Decoder (ID-12) and the Pipeline Sequencer (PS-14). The instruction sequencer can decode and issue up to three instructions per clock. The pipe sequencer (14) employs a write back path to store snap shots of the state of the machine in pipe stages 1 and 2.

Abstract: Logic examines signals from an instruction fetch unit to determine if the next instruction is a branch. A mux selects one of the 4 instruction words. MACRO [0:3] and a displacement from the selected word. A full adder (40) adds this displacement to the instruction pointer. The result is used as the branch address. The timing is such that a 1 clock lookahead is sufficient to hide this calculation from program execution. The branch register address is determined by the process ID and the macro mode state bit. The branch by pass mechanism causes the branch address to be driven from the calculation instead of a branch register. If a branch fail or scoreboard hit occurs, a write cancellation is generated to stop the current address calculation from being stored in a branch register. If a branch fail or scoreboard hit does not occur, then the current address calculation is stored in a branch register. If a branch bypass occurs, then the branch address is driven from the calculation.