Abstract: A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

Abstract: A data transfer controller connected to a first digital interface of a computer system receives an instruction to prepare a plurality of non-contiguous data elements in a memory of the computer system for transfer to a peripheral device connected to the first digital interface. The data elements are read from the memory of the computer system via a plurality of gather transactions on a second digital interface. The second digital interface is connected to the data transfer controller and the memory. The second digital interface allows for use of a subset of overhead data of the first digital interface for the gather transactions. The data elements are written into a contiguous data block in a buffer. An indication that the contiguous data block is available for transfer from the buffer to the peripheral device via the first digital interface is provided to the peripheral device via the first digital interface.

Abstract: A peripheral device includes two or more peripheral-bus modules, a coherent interconnect, and two or more tunnel adapters coupled between the peripheral-bus modules and the coherent interconnect. The peripheral-bus modules are to exchange peripheral-bus packets with one another in accordance with a peripheral-bus protocol. The coherent interconnect is to connect electronic components of the peripheral device in accordance with a coherent interconnect protocol. The tunnel adapters are to convey the peripheral-bus packets between the peripheral-bus modules over the coherent interconnect, by translating between the peripheral-bus packets and messages of the coherent interconnect protocol.

Abstract: A peripheral device includes two or more peripheral-bus modules, a coherent interconnect, and two or more tunnel adapters coupled between the peripheral-bus modules and the coherent interconnect. The peripheral-bus modules are to exchange peripheral-bus packets with one another in accordance with a peripheral-bus protocol. The coherent interconnect is to connect electronic components of the peripheral device in accordance with a coherent interconnect protocol. The tunnel adapters are to convey the peripheral-bus packets between the peripheral-bus modules over the coherent interconnect, by translating between the peripheral-bus packets and messages of the coherent interconnect protocol.

Abstract: A network device includes a packet processing pipeline and handoff circuitry. The packet processing pipeline is to apply to a packet a sequence of commands, one of the commands being a handoff command that diverts processing of the packet to an external device. The handoff circuitry is to generate, in response to the handoff command, an output context indicative of a current processing state of the packet, to send the output context to the external device, to receive from the external device an input context that (i) reflects the processing applied to the packet by the external device and (ii) specifies subsequent processing of the packet by the packet processing pipeline, and to forward the input context to the packet processing pipeline.

Abstract: A peripheral device includes a main chip that includes a coherent interconnect, one or more first peripheral-bus modules, a Chip-to-Chip (C2C) or Die-to-Die (D2D) interface, and one or more tunnel adapters. The coherent interconnect is to connect electronic components of the peripheral device in accordance with a coherent interconnect protocol. The one or more first peripheral-bus modules are to communicate in accordance with a peripheral-bus protocol. The C2C or D2D interface is to communicate over a C2C or D2D bus with an auxiliary chip that includes one or more second peripheral-bus modules. The one or more tunnel adapters are to convey peripheral-bus packets of the peripheral-bus protocol between the first and second peripheral-bus modules over the coherent interconnect and the C2C or D2D bus, by translating between the peripheral-bus packets, messages of the coherent interconnect protocol and C2C or D2D bus messages.

Abstract: Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.

Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.

Abstract: Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.

Abstract: A peripheral device includes two or more peripheral-bus modules, a coherent interconnect, and two or more tunnel adapters coupled between the peripheral-bus modules and the coherent interconnect. The peripheral-bus modules are to exchange peripheral-bus packets with one another in accordance with a peripheral-bus protocol. The coherent interconnect is to connect electronic components of the peripheral device in accordance with a coherent interconnect protocol. The tunnel adapters are to convey the peripheral-bus packets between the peripheral-bus modules over the coherent interconnect, by translating between the peripheral-bus packets and messages of the coherent interconnect protocol.

Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.

Abstract: Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.

Abstract: A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.

Abstract: A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

Abstract: Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.

Abstract: Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results. The input tokens are parsed from network packet headers by a Parser, and the tokens are then modified by the LDE. The modified tokens guide how corresponding network packets will be modified or forwarded by other components in a software-defined networking (SDN) system. The design of the LDE is highly flexible and protocol independent. Conditions and rules for generating lookup keys and for modifying tokens are fully programmable such that the LDE can perform a wide variety of reconfigurable network features and protocols in the SDN system.

Abstract: Embodiments of the present invention are directed to a wildcard matching solution that uses a combination of static random access memories (SRAMs) and ternary content addressable memories (TCAMs) in a hybrid solution. In particular, the wildcard matching solution uses a plurality of SRAM pools for lookup and a spillover TCAM pool for unresolved hash conflicts.

Abstract: A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.

Abstract: A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

Abstract: Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.