Abstract: Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.

Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.

Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.

Abstract: A packet processor includes a header processor and a packet memory. A receive direct memory access block is configured to receive a packet with a header and a payload and to route the header to the header processor and to route the payload to the packet memory such that the header processor begins processing of the header while the payload is loaded into packet memory.

Abstract: A multicast destination table contains a list of links. The list of links includes the main link that is currently in use and alternate links to reach the same destination. The links in the list of links are ordered based on a metric. Each of the links is stored as an entry in the multicast destination table. A multicast replication engine traverses the list of links until an enabled link in the list of links is reached, and replicates a packet according to data associated with the enabled link in the list of links.

Abstract: This disclosure describes techniques and apparatuses enabling low-to-high speed cut-through communication without creating an overrun condition. By so doing, the techniques and/or apparatuses enable communication interfaces to communicate at higher speed, such as by avoiding store-to-forward latency.

Abstract: Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived at. The packets can be distributed for processing within the network chip.

Abstract: A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.

Abstract: Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.

Abstract: Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived at. The packets can be distributed for processing within the network chip.

Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programmed based on how the tiles are allocated for each lookup.

Abstract: A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.

Abstract: A multicast replication engine includes a circuit implemented on a network chip to replicate packets, mirror packets and perform link switchovers. The multicast replication engine determines whether a switchover feature is enabled. If the switchover feature is not enabled, then the multicast replication engine mirrors the packet according to a mirror bit mask and to a mirror destination linked list. The mirror destination linked list corresponds to a mirroring rule. If the switchover feature is enabled, then the multicast replication engine replicates the packet according to a first live link of a failover linked list. The failover linked list corresponds to a switchover rule. The mirroring rule and the switchover rule are stored in the same table. Copies of the packet are forwarded according to a multicast rule that is represented by a hierarchical linked list with N tiers.

Abstract: Embodiments of the present invention relate to a scalable interconnection scheme of multiple processing engines on a single chip using on-chip configurable routers. The interconnection scheme supports unicast and multicast routing of data packets communicated by the processing engines. Each on-chip configurable router includes routing tables that are programmable by software, and is configured to correctly deliver incoming data packets to its output ports in a fair and deadlock-free manner. In particular, each output port of the on-chip configurable routers includes an output port arbiter to avoid deadlocks when there are contentions at output ports of the on-chip configurable routers and to guarantee fairness in delivery among transferred data packets.

Abstract: Embodiments of the apparatus for modifying packet headers relate to pointer structure for splitting a packet into individual layers and for intelligently stitching them back together. The pointer structure includes N+1 layer pointers to N+1 protocol headers. The pointer structure also includes a total size of all headers. A rewrite engine uses the layer pointers to extract the first N corresponding protocol layers within the packet for modification. The rewrite engine uses the layer pointers to form an end point, which together with the total size of all headers is associated with a body of the headers. The body of the headers is a portion of headers that are not modified by the rewrite engine. After all the modifications are performed and modified headers are compressed, the modified layer pointers are used to stitch the modified headers back together with the body of the headers.

Abstract: Embodiments of the apparatus for modifying packet headers relate to programmable modifications of packets by applying commands to generalized protocol headers. Each protocol header of incoming packets is represented in a generic format specific to that protocol to enable modifications to packet headers. Missing fields from a protocol header are detected, and the protocol header is expanded to a maximum size such that the protocol header contains all possible fields of that protocol, including the missing fields. Each of the fields has the same offset irrespective of which variation of the protocol the protocol header corresponds to. Modification uses a set of commands that is applied to expanded protocol headers. All of the commands are thus generic as these commands are independent of incoming headers (e.g., size and protocol).

Abstract: Embodiments of the apparatus for extracting data from packets relate to programmable layer commands that allow fields from packets to be extracted. A packet is split into individual layers. Each layer is given a unique layer type number that identifies the layer. Based on the layer type, each layer is expanded to a generic format. Each layer has a set of layer commands that is generic to that layer. Fields of each layer command are fieldOffset and fieldLen. These layer commands allow information in the packet to be extracted in a programmable manner. Extracted fields from each protocol layer are concatenated to form a token layer. All token layers are concatenated to form a final token, which is used for further processing of the packet.

Abstract: A method includes receiving a packet at an ingress node of a network. A hierarchical time stamp is created in the packet by the ingress node. The hierarchical time stamp includes an initial time stamp and an initial node identifier. The packet is passed to another network node, which adds a subsequent time stamp and a subsequent node identifier to the hierarchical time stamp. The packet is received at an egress node of the network. A final time stamp and a final node identifier are added to the hierarchical time stamp at the egress node. The hierarchical time stamp is then removed from the packet and the packet is passed to another network. The hierarchical time stamp is delivered to an analyzer.

Abstract: Embodiments of the apparatus for modifying packet headers relate to a packet generalization scheme that maintains information across protocol layers of packets. The packet generalization scheme uses a protocol table that includes layer information for all possible protocol layer combinations. The protocol layer combinations in the protocol table are manually configured through software. Each protocol layer combination in the protocol table is uniquely identified by a PktID. A rewrite engine of a network device receives the PktID for a packet and uses that unique identifier as key to the protocol table to access information for each protocol layer of the packet that the rewrite engine requires during modification of the packet. The packet generalization scheme eliminates the need for a parser engine of the network device to pass parsed data to the rewrite engine, which is resource intensive.

Abstract: A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.