Patents by Inventor Tsai-Fu Chen
Tsai-Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250151384Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound semiconductor layer is formed on a first device region and a second device region of a substrate. A III-V compound barrier layer is formed on the III-V compound semiconductor layer. A lamination structure is formed on the III-V compound barrier layer. The lamination structure includes a p-type doped III-V compound layer and a first mask layer disposed thereon. A patterning process is performed to the lamination structure. A first portion of the lamination structure located above the first device region is patterned by the patterning process. A second portion of the lamination structure located above the second device region is removed by the patterning process. A thickness of the second portion of the lamination structure is greater than a thickness of the first portion of the lamination structure before the patterning process.Type: ApplicationFiled: December 14, 2023Publication date: May 8, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shuo-Lin Hsu, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen
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Patent number: 12100756Abstract: A high electron mobility transistor (HEMT) device including a substrate, a channel layer, a barrier layer, a p-type gallium nitride (GaN) spacer, a gate electrode, a source electrode, and a drain electrode is provided. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer and has a protruding portion. The P-type GaN spacer is disposed on a side wall of the protruding portion. The gate electrode is disposed on the protruding portion and the P-type GaN spacer. The source electrode and the drain electrode are disposed on two sides of the gate electrode.Type: GrantFiled: November 16, 2021Date of Patent: September 24, 2024Assignee: United Microelectronics Corp.Inventors: Hao-Ming Lee, Ta Kang Lo, Tsai-Fu Chen, Shou-Wei Hsieh
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Publication number: 20230129579Abstract: A high electron mobility transistor (HEMT) device including a substrate, a channel layer, a barrier layer, a p-type gallium nitride (GaN) spacer, a gate electrode, a source electrode, and a drain electrode is provided. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer and has a protruding portion. The P-type GaN spacer is disposed on a side wall of the protruding portion. The gate electrode is disposed on the protruding portion and the P-type GaN spacer. The source electrode and the drain electrode are disposed on two sides of the gate electrode.Type: ApplicationFiled: November 16, 2021Publication date: April 27, 2023Applicant: United Microelectronics Corp.Inventors: Hao-Ming Lee, Ta Kang Lo, Tsai-Fu Chen, Shou-Wei Hsieh
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Patent number: 9779998Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.Type: GrantFiled: March 6, 2017Date of Patent: October 3, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Chen Tsai, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
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Publication number: 20170221766Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.Type: ApplicationFiled: March 6, 2017Publication date: August 3, 2017Inventors: Chia-Chen Tsai, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
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Patent number: 9685520Abstract: A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.Type: GrantFiled: November 17, 2016Date of Patent: June 20, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shuo-Lin Hsu, Hsin-Ta Hsieh, Chun-Chia Chen, Chen-Chien Li, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
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Patent number: 9634002Abstract: A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.Type: GrantFiled: February 29, 2016Date of Patent: April 25, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Chen Tsai, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
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Patent number: 8823109Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.Type: GrantFiled: January 9, 2013Date of Patent: September 2, 2014Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
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Patent number: 8765561Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.Type: GrantFiled: June 6, 2011Date of Patent: July 1, 2014Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Ta-Kang Lo, Tzyy-Ming Cheng
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Patent number: 8735268Abstract: A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed.Type: GrantFiled: June 22, 2011Date of Patent: May 27, 2014Assignee: United Microelectronics Corp.Inventors: Ching-Sen Lu, Wen-Han Hung, Tsai-Fu Chen, Tzyy-Ming Cheng
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Patent number: 8486795Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.Type: GrantFiled: April 12, 2012Date of Patent: July 16, 2013Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
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Patent number: 8404533Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.Type: GrantFiled: August 23, 2010Date of Patent: March 26, 2013Assignee: United Microelectronics Corp.Inventors: Cheng-Yu Ma, Wen-Han Hung, Ta-Kang Lo, Tsai-Fu Chen, Tzyy-Ming Cheng
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Patent number: 8390073Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.Type: GrantFiled: April 18, 2012Date of Patent: March 5, 2013Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
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Publication number: 20120329259Abstract: A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed.Type: ApplicationFiled: June 22, 2011Publication date: December 27, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Sen LU, Wen-Han HUNG, Tsai-Fu CHEN, Tzyy-Ming CHENG
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Publication number: 20120309158Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.Type: ApplicationFiled: June 6, 2011Publication date: December 6, 2012Inventors: Wen-Han Hung, Tsai-Fu Chen, Ta-Kang Lo, Tzyy-Ming Cheng
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Publication number: 20120289015Abstract: A method for fabricating a semiconductor device with enhanced channel stress is provided. The method includes the following steps. Firstly, a substrate is provided. Then, at least one source/drain region and a channel are formed in the substrate. A dummy gate is formed over the channel. A contact structure is formed over the source/drain region. After the contact structure is formed, the dummy gate is removed to form a trench.Type: ApplicationFiled: May 13, 2011Publication date: November 15, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Sen Lu, Wen-Han Hung, Tsai-Fu Chen, Tzyy-Ming Cheng
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Publication number: 20120199890Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.Type: ApplicationFiled: April 18, 2012Publication date: August 9, 2012Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
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Publication number: 20120196418Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.Type: ApplicationFiled: April 12, 2012Publication date: August 2, 2012Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
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Patent number: 8211775Abstract: A method for forming a transistor having a metal gate is provided. A substrate is provided first. A transistor is formed on the substrate. The transistor includes a high-k gate dielectric layer, an oxygen containing dielectric layer disposed on the high-k gate dielectric layer, and a dummy gate disposed on the oxygen containing dielectric layer. Then, the dummy gate and the patterned gate dielectric layer are removed. Lastly, a metal gate is formed and the metal gate directly contacts the high-k gate oxide.Type: GrantFiled: March 9, 2011Date of Patent: July 3, 2012Assignee: United Microelectronics Corp.Inventors: Cheng-Yu Ma, Wen-Han Hung, Ta-Kang Lo, Tsai-Fu Chen, Tzyy-Ming Cheng
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Patent number: 8183640Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.Type: GrantFiled: July 14, 2009Date of Patent: May 22, 2012Assignee: United Microelectronics Corp.Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng