Patents by Inventor Tsai-Fu Chen

Tsai-Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9779998
    Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Chen Tsai, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
  • Publication number: 20170221766
    Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.
    Type: Application
    Filed: March 6, 2017
    Publication date: August 3, 2017
    Inventors: Chia-Chen Tsai, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
  • Patent number: 9685520
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first gate dielectric layer is formed in a first gate trench and a second gate dielectric layer is formed in a second gate trench. A first bottom barrier layer is formed on the first gate dielectric layer and the second gate dielectric layer. A first conductivity type work function layer is formed on the first bottom barrier layer. A first treatment to the first gate dielectric layer and/or a second treatment to the first bottom barrier layer on the first gate dielectric layer are performed before the step of forming the first conductivity type work function layer. The first treatment and the second treatment are used to modify threshold voltages of specific transistors, and thicknesses of work function layers formed subsequently may be modified for increasing the related process window accordingly.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shuo-Lin Hsu, Hsin-Ta Hsieh, Chun-Chia Chen, Chen-Chien Li, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
  • Patent number: 9634002
    Abstract: A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: April 25, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Chen Tsai, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen
  • Patent number: 8823109
    Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 2, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
  • Patent number: 8765561
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: July 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Tsai-Fu Chen, Ta-Kang Lo, Tzyy-Ming Cheng
  • Patent number: 8735268
    Abstract: A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: May 27, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Sen Lu, Wen-Han Hung, Tsai-Fu Chen, Tzyy-Ming Cheng
  • Patent number: 8486795
    Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: July 16, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
  • Patent number: 8404533
    Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 26, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yu Ma, Wen-Han Hung, Ta-Kang Lo, Tsai-Fu Chen, Tzyy-Ming Cheng
  • Patent number: 8390073
    Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: March 5, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
  • Publication number: 20120329259
    Abstract: A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 27, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Sen LU, Wen-Han HUNG, Tsai-Fu CHEN, Tzyy-Ming CHENG
  • Publication number: 20120309158
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 6, 2012
    Inventors: Wen-Han Hung, Tsai-Fu Chen, Ta-Kang Lo, Tzyy-Ming Cheng
  • Publication number: 20120289015
    Abstract: A method for fabricating a semiconductor device with enhanced channel stress is provided. The method includes the following steps. Firstly, a substrate is provided. Then, at least one source/drain region and a channel are formed in the substrate. A dummy gate is formed over the channel. A contact structure is formed over the source/drain region. After the contact structure is formed, the dummy gate is removed to form a trench.
    Type: Application
    Filed: May 13, 2011
    Publication date: November 15, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Sen Lu, Wen-Han Hung, Tsai-Fu Chen, Tzyy-Ming Cheng
  • Publication number: 20120199890
    Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a P-type well, a gate disposed on the P-type well, a first spacer disposed on the gate, an N-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the N-type source/drain region, a second spacer around the first spacer and the second spacer directly on and covering a portion of the silicon cap layer and a silicide layer disposed on the silicon cap layer.
    Type: Application
    Filed: April 18, 2012
    Publication date: August 9, 2012
    Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
  • Publication number: 20120196418
    Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.
    Type: Application
    Filed: April 12, 2012
    Publication date: August 2, 2012
    Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
  • Patent number: 8211775
    Abstract: A method for forming a transistor having a metal gate is provided. A substrate is provided first. A transistor is formed on the substrate. The transistor includes a high-k gate dielectric layer, an oxygen containing dielectric layer disposed on the high-k gate dielectric layer, and a dummy gate disposed on the oxygen containing dielectric layer. Then, the dummy gate and the patterned gate dielectric layer are removed. Lastly, a metal gate is formed and the metal gate directly contacts the high-k gate oxide.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: July 3, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yu Ma, Wen-Han Hung, Ta-Kang Lo, Tsai-Fu Chen, Tzyy-Ming Cheng
  • Patent number: 8183640
    Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: May 22, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
  • Publication number: 20120086054
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a gate structure disposed on a substrate, a source and a drain respectively disposed in the substrate at two sides of the gate structure, a source contact plug disposed above the source and electrically connected to the source and a drain contact plug disposed above the drain and electrically connected to the drain. The source contact plug and the drain contact plug have relatively asymmetric element properties.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 12, 2012
    Inventors: Tzyy-Ming Cheng, Meng-Chi Tsai, Tsai-Fu Chen, Ta-Kang Lo, Wen-Han Hung, Shih-Fang Tzou, Chun-Yuan Wu
  • Publication number: 20120070948
    Abstract: An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a source/drain region, a channel, a gate, a gate dielectric layer and a spacer. A dielectric layer is formed on the substrate and covers the metal-oxide-semiconductor field-effect transistor. A flattening process is applied onto the dielectric layer. The remaining dielectric layer is removed to expose the source/drain region. A non-conformal high stress dielectric layer is formed on the substrate having the exposed source/drain region.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tzyy-Ming CHENG, Ching-Sen Lu, Tsai-Fu Chen, Wen-Han Hung, Ta-Kang Lo, Chun-Yuan Wu, Shih-Fang Tzou
  • Publication number: 20120045880
    Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.
    Type: Application
    Filed: August 23, 2010
    Publication date: February 23, 2012
    Inventors: Cheng-Yu Ma, Wen-Han Hung, Ta-Kang Lo, Tsai-Fu Chen, Tzyy-Ming Cheng