Patents by Inventor Tsai-Fu Hsiao
Tsai-Fu Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220181143Abstract: An apparatus includes a vacuum chamber, a wafer transfer mechanism, a first gas source, a second gas source and a reuse gas pipe. The vacuum chamber is divided into at least three reaction regions including a first reaction region, a second reaction region and a third reaction region. The wafer transfer mechanism is structured to transfer a wafer from the first reaction region to the third reaction region via the second reaction region. The first gas source supplies a first gas to the first reaction region via a first gas pipe, and a second gas source supplies a second gas to the second reaction region via a second gas pipe. The reuse gas pipe is connected between the first reaction region and the third reaction region for supplying an unused first gas collected in the first reaction region to the third reaction region.Type: ApplicationFiled: February 3, 2022Publication date: June 9, 2022Inventors: Tsai-Fu HSIAO, Kuang-Yuan HSU, Pei-Ren JENG, Tze-Liang LEE
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Patent number: 11244822Abstract: An apparatus includes a vacuum chamber, a wafer transfer mechanism, a first gas source, a second gas source and a reuse gas pipe. The vacuum chamber is divided into at least three reaction regions including a first reaction region, a second reaction region and a third reaction region. The wafer transfer mechanism is structured to transfer a wafer from the first reaction region to the third reaction region via the second reaction region. The first gas source supplies a first gas to the first reaction region via a first gas pipe, and a second gas source supplies a second gas to the second reaction region via a second gas pipe. The reuse gas pipe is connected between the first reaction region and the third reaction region for supplying an unused first gas collected in the first reaction region to the third reaction region.Type: GrantFiled: October 20, 2015Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsai-Fu Hsiao, Kuang-Yuan Hsu, Pei-Ren Jeng, Tze-Liang Lee
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Publication number: 20170110312Abstract: An apparatus includes a vacuum chamber, a wafer transfer mechanism, a first gas source, a second gas source and a reuse gas pipe. The vacuum chamber is divided into at least three reaction regions including a first reaction region, a second reaction region and a third reaction region. The wafer transfer mechanism is structured to transfer a wafer from the first reaction region to the third reaction region via the second reaction region. The first gas source supplies a first gas to the first reaction region via a first gas pipe, and a second gas source supplies a second gas to the second reaction region via a second gas pipe. The reuse gas pipe is connected between the first reaction region and the third reaction region for supplying an unused first gas collected in the first reaction region to the third reaction region.Type: ApplicationFiled: October 20, 2015Publication date: April 20, 2017Inventors: Tsai-Fu HSIAO, Kuang-Yuan HSU, Pei-Ren JENG, Tze-Liang LEE
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Patent number: 9607826Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.Type: GrantFiled: April 13, 2015Date of Patent: March 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gin-Chen Huang, Tsai-Fu Hsiao, Ching-Hong Jiang, Neng-Kuo Chen, Hongfa Luan, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9502305Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.Type: GrantFiled: October 22, 2013Date of Patent: November 22, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Wei Chen, Teng-Chun Tsai, Chien-Chung Huang, Jei-Ming Chen, Tsai-Fu Hsiao
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Patent number: 9228260Abstract: A wafer processing chamber is provided, including a first processing gas supply unit and a second processing gas supply unit. The first processing gas supply unit is configured for supplying a first processing gas to form a first processing zone in the wafer processing chamber. The second processing gas supply unit is configured for supplying a second processing gas into the wafer processing chamber to form a second processing zone in the wafer processing chamber. In the wafer processing chamber, the first processing zone and the second processing zone are virtually separated from each other, such that a process wafer in the first processing zone may be performed a different process from another process wafer in the second processing zone at the same time. Further, a heat treatment apparatus and a method for processing wafers also provide herein.Type: GrantFiled: July 30, 2014Date of Patent: January 5, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsai-Fu Hsiao, Chun-Yao Wang, Tai-Chun Huang, Tze-Liang Lee
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Publication number: 20150221504Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.Type: ApplicationFiled: April 13, 2015Publication date: August 6, 2015Inventors: Gin-Chen Huang, Tsai-Fu Hsiao, Ching-Hong Jiang, Neng-Kuo Chen, Hongfa Luan, Sey-Ping Sung, Clement Hsingjen Wann
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Patent number: 9006802Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.Type: GrantFiled: August 18, 2011Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gin-Chen Huang, Tsai-Fu Hsiao, Ching-Hong Jiang, Neng-Kuo Chen, Hongfa Luan, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20140038374Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.Type: ApplicationFiled: October 22, 2013Publication date: February 6, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Wei Chen, Teng-Chun Tsai, Chien-Chung Huang, Jei-Ming Chen, Tsai-Fu Hsiao
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Publication number: 20130043512Abstract: Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.Type: ApplicationFiled: August 18, 2011Publication date: February 21, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gin-Chen Huang, Tsai-Fu Hsiao, Ching-Hong Jiang, Neng-Kuo Chen, Hongfa Luan, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20120202328Abstract: The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.Type: ApplicationFiled: April 19, 2012Publication date: August 9, 2012Inventors: Tsuo-Wen Lu, Tsai-Fu Hsiao, Yu-Ren Wang, Shu-Yen Chan
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Patent number: 8183118Abstract: The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.Type: GrantFiled: August 26, 2010Date of Patent: May 22, 2012Assignee: United Microelectronics Corp.Inventors: Tsuo-Wen Lu, Tsai-Fu Hsiao, Yu-Ren Wang, Shu-Yen Chan
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Publication number: 20120068268Abstract: A method of fabricating a transistor structure includes the step of providing a substrate having a gate thereon. Then, a first spacer is formed at two sides of the gate. After that, an LDD region is formed in the substrate at two sides of the gate. Later, a second spacer comprising a carbon-containing spacer and a sacrificing spacer is formed on the first spacer. Subsequently, a source/drain region is formed in the substrate at two sides of the gate. Finally, the sacrificing spacer is removed entirely, and part of the carbon-containing spacer is also removed. The remaining carbon-containing spacer has an L shape. The carbon-containing spacer has a first carbon concentration, and the sacrificing spacer has a second carbon concentration. The first carbon concentration is greater than the second carbon concentration.Type: ApplicationFiled: September 22, 2010Publication date: March 22, 2012Inventors: Tsai-Fu Hsiao, Tsuo-Wen Lu, Yu-Ren Wang
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Publication number: 20120052644Abstract: The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.Type: ApplicationFiled: August 26, 2010Publication date: March 1, 2012Inventors: Tsuo-Wen Lu, Tsai-Fu Hsiao, Yu-Ren Wang, Shu-Yen Chan
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Patent number: 8076210Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.Type: GrantFiled: March 8, 2011Date of Patent: December 13, 2011Assignee: United Microelectronics Corp.Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
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Patent number: 8053847Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.Type: GrantFiled: November 28, 2008Date of Patent: November 8, 2011Assignee: United Microelectronics Corp.Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
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Publication number: 20110159658Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
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Patent number: 7927954Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.Type: GrantFiled: February 26, 2007Date of Patent: April 19, 2011Assignee: United Microelectronics Corp.Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Wen-Han Hung, Tzyy-Ming Cheng, Meng-Yi Wu, Tsai-Fu Hsiao, Shu-Yen Chan
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Patent number: 7892935Abstract: A semiconductor process is provided. The semiconductor process includes providing a substrate. Then, a surface treatment is performed to the substrate to form a buffer layer on the substrate. Next, a first pre-amorphous implantation is performed to the substrate.Type: GrantFiled: November 30, 2006Date of Patent: February 22, 2011Assignee: United Microelectronics Corp.Inventors: Yi-Wei Chen, Chao-Ching Hsieh, Tsai-Fu Hsiao, Yu-Lan Chang, Tsung-Yu Hung, Chun-Chieh Chang
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Patent number: 7795101Abstract: A method of forming a MOS transistor, in which, a co-implantation is performed to implant a carbon co-implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect, and the carbon co-implant is from a precursor comprising CO or CO2.Type: GrantFiled: February 8, 2010Date of Patent: September 14, 2010Assignee: United Microelectronics Corp.Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen