Patents by Inventor Tsai-Fu Hsiao

Tsai-Fu Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100144110
    Abstract: A method of forming a MOS transistor, in which, a co-implantation is performed to implant a carbon co-implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect, and the carbon co-implant is from a precursor comprising CO or CO2.
    Type: Application
    Filed: February 8, 2010
    Publication date: June 10, 2010
    Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
  • Publication number: 20100001317
    Abstract: A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 7, 2010
    Inventors: Yi-Wei Chen, Teng-Chun Tsai, Chien-Chung Huang, Jei-Ming Chen, Tsai-Fu Hsiao
  • Patent number: 7553763
    Abstract: A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting the metal layer with the amorphized layer to form a silicide layer on the surface of the silicon substrate.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: June 30, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Fu Hsiao, Chin-Cheng Chien, Kuo-Tai Huang
  • Patent number: 7550336
    Abstract: A method for fabricating an NMOS transistor is disclosed. First, a substrate having a gate structure thereon is provided. A carbon implantation process is performed thereafter by implanting carbon atoms into the substrate for forming a silicon carbide region in the substrate. Subsequently, a source/drain region is formed surrounding the gate structure. By conducting a carbon implantation process into the substrate and a corresponding amorphorized implantation process before or after the carbon implantation process is completed, the present invention eliminates the need of forming a recess for accommodating an epitaxial layer composed of silicon carbide while facilitates the formation of silicon carbide from the combination of both implantation processes.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: June 23, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Fu Hsiao, Po-Yuan Chen, Jung-Chin Chen
  • Publication number: 20090101894
    Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.
    Type: Application
    Filed: November 28, 2008
    Publication date: April 23, 2009
    Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
  • Patent number: 7473606
    Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: January 6, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
  • Publication number: 20080258178
    Abstract: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of CO, CO2, CxHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of to 1000.
    Type: Application
    Filed: May 27, 2008
    Publication date: October 23, 2008
    Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
  • Publication number: 20080206942
    Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.
    Type: Application
    Filed: February 26, 2007
    Publication date: August 28, 2008
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Wen-Han Hung, Tzyy-Ming Cheng, Meng-Yi Wu, Tsai-Fu Hsiao, Shu-Yen Chan
  • Patent number: 7396717
    Abstract: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, Chd xHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: July 8, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
  • Publication number: 20080132023
    Abstract: A semiconductor process is provided. The semiconductor process includes providing a substrate. Then, a surface treatment is performed to the substrate to form a buffer layer on the substrate. Next, a first pre-amorphous implantation is performed to the substrate.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 5, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Wei Chen, Chao-Ching Hsieh, Tsai-Fu Hsiao, Yu-Lan Chang, Tsung-Yu Hung, Chun-Chieh Chang
  • Publication number: 20070238234
    Abstract: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, CxHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.
    Type: Application
    Filed: April 3, 2006
    Publication date: October 11, 2007
    Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
  • Publication number: 20070228464
    Abstract: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, CxHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.
    Type: Application
    Filed: May 14, 2007
    Publication date: October 4, 2007
    Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
  • Publication number: 20070196990
    Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.
    Type: Application
    Filed: February 15, 2007
    Publication date: August 23, 2007
    Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
  • Publication number: 20070122987
    Abstract: A method for fabricating an NMOS transistor is disclosed. First, a substrate having a gate structure thereon is provided. A carbon implantation process is performed thereafter by implanting carbon atoms into the substrate for forming a silicon carbide region in the substrate. Subsequently, a source/drain region is formed surrounding the gate structure. By conducting a carbon implantation process into the substrate and a corresponding amorphorized implantation process before or after the carbon implantation process is completed, the present invention eliminates the need of forming a recess for accommodating an epitaxial layer composed of silicon carbide while facilitates the formation of silicon carbide from the combination of both implantation processes.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 31, 2007
    Inventors: Tsai-Fu Hsiao, Po-Yuan Chen, Jung-Chin Chen
  • Publication number: 20070037373
    Abstract: A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting the metal layer with the amorphized layer to form a silicide layer on the surface of the silicon substrate.
    Type: Application
    Filed: August 8, 2006
    Publication date: February 15, 2007
    Inventors: Tsai-Fu Hsiao, Chin-Cheng Chien, Kuo-Tai Huang
  • Publication number: 20060062913
    Abstract: A chemical vapor deposition (CVD) system comprises a tubular furnace, at least one BTBAS supply piping line connected to a base portion of the tubular furnace, an exhaust piping line connected to an upper portion of the tubular furnace, a bypass line connecting the BTBAS supply piping line with the exhaust piping line, and a vacuum pump connected to the exhaust piping line, wherein the bypass line is initially interrupted. A batch of wafers is placed into a tube of the tubular furnace. Nitrogen-containing gas and carrier gas are flowed into the tube. BTBAS is flowed into the tube through the BTBAS supply piping line. A silicon nitride deposition process is then carried out in the tube to deposit a BTBAS-based silicon nitride film on the wafers. Upon completion of the silicon nitride deposition process, the BTBAS supply piping line is blocked and the initially interrupted bypass line is opened.
    Type: Application
    Filed: September 17, 2004
    Publication date: March 23, 2006
    Inventors: Yun-Ren Wang, Ying-Wei Yen, Hao-Hsiang Chang, Tsai-Fu Hsiao
  • Patent number: 6112013
    Abstract: A method and an apparatus for detecting the crack of a heater of an acid and rinse bath, acid and rinse bath is filled with acid solution, a heater is used to heat the acid solution. A heater is constituted of a hollow quartz tube with one closed end and one open end, the closed end is submerged into acid solution, part of the quartz tube is exposure in the air. The heated filament is inserted into the open end of the heater through the closed end of the heater, moisture detecting device is attached on the inner side wall of the quartz tube, use chemicals that will change color by absorbing moisture, or use electronic component to detect the humidity, monitoring the variation of moisture in the quartz tube to acknowledge is there any crack of the quartz tube, and replace the defect quartz tube before too late.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: August 29, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-fu Hsiao, Yu-Shaw Tai, Kuo Tung-Chu