Abstract: A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers is deposited on sidewalls of each first spacer. In some embodiments, a spacing between adjacent first spacers is configured such that second spacers formed on sidewalls of the adjacent first spacers physically merge to form a merged second spacer. A second spacer cut process may be performed to selectively remove at least one second spacer. In some embodiments, a third spacer of a plurality of third spacers is formed on sidewalls of each second spacer. A third spacer cut process may be performed to selectively remove at least one third spacer. A first etch process is performed on the substrate to form fin regions. The plurality of third spacers mask portions of the substrate during the first etch process.

Abstract: A method for fabricating a semiconductor device includes forming a hard mask (HM) layer over a material layer, forming a first trench in the HM layer, which extends along a first direction. The method also includes forming a first patterned resist layer over the HM layer. The first patterned resist layer has a first opening and a second opening a second direction. The first opening overlaps with the first trench in a middle portion of the first trench and the second opening overlaps with the first trench at an end portion of the first trench. The method also includes etching the HM layer through the first patterned resist layer to form a second trench and a third trench in the HM layer and forming a first feature to fill in a section of the first trench between the second trench and the third trench.

Abstract: The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects.

Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Abstract: A method for fabricating a semiconductor device includes forming a hard mask (HM) layer over a material layer, forming a first trench in the HM layer, which extends along a first direction. The method also includes forming a first patterned resist layer over the HM layer. The first patterned resist layer has a first opening and a second opening a second direction. The first opening overlaps with the first trench in a middle portion of the first trench and the second opening overlaps with the first trench at an end portion of the first trench. The method also includes etching the HM layer through the first patterned resist layer to form a second trench and a third trench in the HM layer and forming a first feature to fill in a section of the first trench between the second trench and the third trench.

Abstract: The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second width, around a first and a second desired layout feature pattern of the desired layout over a semiconductor substrate. The first desired layout feature pattern is formed using a first sub-layout and the second desired layout feature pattern is formed using a second sub-layout. The first and second desired layout feature patterns are separated by a first width. The method further includes forming a third desired layout feature pattern according to a third sub-layout. The third desired layout feature pattern is shaped in part by the spacer. The method further includes removing the spacer from around the first and second desired layout feature pattern and etching the target layer using the first, second, and third layout feature patterns as masking features.

Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of: forming a plurality of first features over the target material layer using a first sub-layout, with each first feature having sidewalls; forming a plurality of spacer features, with each spacer feature conforming to the sidewalls of one of the first features and having a spacer width; and forming a plurality of second features over the target material layer using a second sub-layout. The method further includes steps of removing the plurality of spacer features from around each first feature and patterning the target material layer using the plurality of first features and the plurality of second features. Other methods and associated patterned semiconductor wafers are also provided herein.

Abstract: The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.

Abstract: Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material.

Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Abstract: A method including forming a trench over a layer disposed on a semiconductor substrate. The trench is filled with a first material to form a filled trench. A feature of a second material is formed over the filled trench. The feature is disposed over the filled trench and extends along two opposing sidewalls of the filled trench to a top surface of the layer. The feature is then planarized to expose a top surface of the filled trench and provide a first portion of the feature adjacent a first sidewall of the two opposing sidewalls of the filled trench and a second portion of the feature adjacent a second sidewall of the two opposing sidewalls of the filled trench. The first and second portions of the feature are used to define a dimension of an interconnect feature disposed over the semiconductor substrate.

Abstract: A photomask and method for fabricating an integrated circuit is provided. The photomask includes a plurality of main features, enclosed in at least one first region and at least one second region, wherein the first region comprises single the main feature and the second region comprises multiple the main features; and a plurality of assistant features disposed between the first region and the second region, or between the second regions. The photomask enhances the accuracy of the critical dimension and facilitate fabricating an integrated circuit.

Abstract: The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.

Abstract: A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.

Abstract: A method includes forming a first material layer on a substrate and performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer. The method further includes performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, wherein the second layout a cut pattern for the first layout. The method further includes forming spacer features on sidewalls of both the first and second pluralities of trenches, wherein the spacer features have a thickness and the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features. The method further includes removing the first material layer; forming a second material layer on the substrate and within openings defined by the spacer features; and removing the spacer features.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns.

Abstract: A system for overlay offset measurement in semiconductor manufacturing including a radiation source, a detector, and a calculation unit. The radiation source is operable to irradiate an overlay offset measurement target. The detector is operable to detect a first reflectivity and a second reflectivity of the irradiated overlay offset measurement target. The calculation unit is operable to determine an overlay offset using the detected first and second reflectivity by determining a predetermined overlay offset amount which provides an actual offset of zero.