Patents by Inventor Tsai Yu-Wen

Tsai Yu-Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9882022
    Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, a gate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 30, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Fu-Yu Tsai
  • Patent number: 9871136
    Abstract: A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Cheng Chen, Tsai-Yu Wen, Shan Ye, Tsuo-Wen Lu
  • Patent number: 9859164
    Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Shiou Hsieh, Chun-Yao Yang, Shi-You Liu, Rong-Sin Lin, Han-Ting Yen, Neng-Hui Yang, Tsai-Yu Wen, Ching-I Li
  • Publication number: 20170358684
    Abstract: A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.
    Type: Application
    Filed: July 11, 2016
    Publication date: December 14, 2017
    Inventors: Shih-Cheng Chen, Tsai-Yu Wen, Shan Ye, Tsuo-Wen Lu
  • Publication number: 20170243952
    Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.
    Type: Application
    Filed: May 10, 2017
    Publication date: August 24, 2017
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Fu-Yu Tsai
  • Patent number: 9735235
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: August 15, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Patent number: 9685533
    Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.
    Type: Grant
    Filed: February 21, 2016
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Fu-Yu Tsai
  • Patent number: 9653549
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 16, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun Jen Chen, Bin-Siang Tsai, Tsai-Yu Wen, Yu Shu Lin, Chin-Sheng Yang
  • Publication number: 20160329400
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Application
    Filed: July 21, 2016
    Publication date: November 10, 2016
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20160276431
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 22, 2016
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20160276434
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.
    Type: Application
    Filed: May 27, 2016
    Publication date: September 22, 2016
    Inventors: Chun Jen Chen, Bin-Siang Tsai, Tsai-Yu Wen, Yu Shu Lin, Chin-Sheng Yang
  • Patent number: 9431483
    Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 30, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsai-Yu Wen, Chin-Sheng Yang, Chun-Jen Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Patent number: 9379182
    Abstract: A method for forming germanium nanowires comprises forming a semiconductor fin structure including alternating fin and shallow trench structures, etching a top portion of the fin to form a fin recess and depositing a germanium-based semiconductor into the fin recess as a germanium-based plug. The method comprises etching the shallow trench structure to expose the germanium-based semiconductor side faces. The exposed germanium-based semiconductor undergoes annealing to form high carrier mobility nanowire structures. The nanowire structures can also be formed of different diameters by selective oxidation of some of the deposited germanium-based plugs. Alternately, forming fin structures of different widths results in deposited germanium plugs of different widths to be deposited to form different thicknesses of nanowires.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun Jen Chen, Bin-Siang Tsai, Tsai-Yu Wen, Yu Shu Lin, Chin-Sheng Yang
  • Patent number: 9349599
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Feng Ku, Shao-Wei Wang, Yi-Hui Lin, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
  • Publication number: 20160133474
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having gate structure thereon, wherein the gate structure comprises a high-k dielectric layer; increasing an ambient pressure around the gate structure to a predetermined pressure by injecting a first gas; reducing the ambient pressure to a base pressure; and forming a spacer around the gate structure.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 12, 2016
    Inventors: Chih-Feng Ku, Shao-Wei Wang, Yi-Hui Lin, Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang
  • Patent number: 9330902
    Abstract: A method for forming a HfOx film based on atomic layer deposition (ALD) process includes: providing a substrate; dividing a plurality of ALD cycles as needed into multiple depositing stages, wherein each of the ALD cycles includes applying HfCl4 pulse and applying H2O pulse over the substrate and a content ratio of HfCl4 to H2O is different and increasing for the depositing stages; and performing the depositing stages to form a HfOx film.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: May 3, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Shih-Cheng Chen, Shan Ye, Tsuo-Wen Lu, Yu-Ren Wang
  • Patent number: 9117878
    Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: August 25, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Keng-Jen Lin, Yu-Ren Wang, Chih-Chung Chen, Tsuo-Wen Lu, Tsai-Yu Wen
  • Patent number: 9034705
    Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: May 19, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
  • Patent number: 9012324
    Abstract: A through silicon via process includes the following steps. A substrate having a front side and a back side is provided. A passivation layer is formed on the back side of the substrate. An oxide layer is formed on the passivation layer.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Jia-Jia Chen, Chi-Mao Hsu, Tsun-Min Cheng, Ching-Wei Hsu, Szu-Hao Lai, Huei-Ru Tsai, Tsai-Yu Wen, Ching-Li Yang, Chien-Li Kuo
  • Patent number: 8853060
    Abstract: An epitaxial process includes the following step. A recess is formed in a substrate. A seeding layer is formed to cover a surface of the recess. A buffer layer is formed on the seeding layer. An etching process is performed on the buffer layer to homogenize and shape the buffer layer. An epitaxial layer is formed on the homogenized flat bottom shape buffer layer.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: October 7, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Szu-Hao Lai, Chun-Yuan Wu, Chin-Cheng Chien, Tien-Wei Yu, Ming-Hua Chang, Yu-Shu Lin, Tsai-Yu Wen, Hsin-Kuo Hsu