Patents by Inventor Tsang-Jiuh Wu

Tsang-Jiuh Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10396014
    Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: August 27, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20190259684
    Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.
    Type: Application
    Filed: May 3, 2019
    Publication date: August 22, 2019
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20190252312
    Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
    Type: Application
    Filed: September 4, 2018
    Publication date: August 15, 2019
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh
  • Patent number: 10290604
    Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Tsang-Jiuh Wu, Cheng-Chieh Hsieh
  • Publication number: 20190122927
    Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Jiung Wu, Kuan-Liang Lai, Ming-Tsu Chung, Hong-Ye Shih, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Publication number: 20190067107
    Abstract: A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 28, 2019
    Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
  • Patent number: 10163705
    Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiung Wu, Kuan-Liang Lai, Ming-Tsu Chung, Hong-Ye Shih, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 10157866
    Abstract: A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20180350778
    Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.
    Type: Application
    Filed: July 26, 2018
    Publication date: December 6, 2018
    Inventors: Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10115634
    Abstract: A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10074595
    Abstract: An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ku-Feng Yang, Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai, Hsin-Yu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10032698
    Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsiao Yun Lo, Yung-Chi Lin, Yang-Chih Hsueh, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20180145012
    Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 24, 2018
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20180145022
    Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.
    Type: Application
    Filed: November 2, 2017
    Publication date: May 24, 2018
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20180145046
    Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 24, 2018
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 9978607
    Abstract: A device comprises a via in a substrate comprising a lower via portion with a first width formed of a first conductive material and an upper via portion with a second width greater than the first width, wherein the upper via portion comprises a protection layer formed of the first conductive material and a via fill material portion formed of a second conductive material.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hung-Pin Chang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20180114770
    Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.
    Type: Application
    Filed: December 11, 2017
    Publication date: April 26, 2018
    Inventors: Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Tsang-Jiuh Wu, Cheng-Chieh Hsieh
  • Patent number: 9953920
    Abstract: An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first photo-sensitive dielectric layer formed over the interlayer dielectric layer, wherein the first photo-sensitive dielectric layer comprises a first metal structure and a second photo-sensitive dielectric layer formed over the first photo-sensitive dielectric, wherein the second photo-sensitive dielectric layer comprises a second metal structure having a bottom surface coplanar with a top surface of the first metal structure.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yu Chen, Ku-Feng Yang, Tasi-Jung Wu, Lin-Chih Huang, Yuan-Hung Liu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20180012825
    Abstract: An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Inventors: Ku-Feng Yang, Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai, Hsin-Yu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 9865523
    Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou