Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

Abstract: A semiconductor device includes a photonic die and an optical die. The photonic die includes a grating coupler and an optical device. The optical device is connected to the grating coupler to receive radiation of predetermined wavelength incident on the grating coupler. The optical die is disposed over the photonic die and includes a substrate with optical nanostructures. Positions and shapes of the optical nanostructures are such to perform an optical transformation on the incident radiation of predetermined wavelength when the incident radiation passes through an area of the substrate where the optical nanostructures are located. The optical nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optical die where the optical nanostructures are located before reaching the grating coupler.

Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Abstract: A manufacturing method of a semiconductor structure is provided. The method includes: forming contact pads on an interconnect structure over a semiconductor substrate; forming a dielectric material stack on the interconnect structure; forming holes and a recess in the dielectric material stack to form a dielectric structure, wherein the holes accessibly expose portions of the contact pads, and the recess is formed between adjacent two of the holes; and forming conductive materials in the holes and the recess to respectively form bonding connectors and a dummy feature. The bonding connectors land on the contact pads, and the dummy feature is isolated and substantially equidistant from adjacent two of the bonding connectors.

Abstract: A semiconductor device includes a photonic die and an optical die. The photonic die includes a grating coupler and an optical device. The optical device is connected to the grating coupler to receive radiation of predetermined wavelength incident on the grating coupler. The optical die is disposed over the photonic die and includes a substrate with optical nanostructures. Positions and shapes of the optical nanostructures are such to perform an optical transformation on the incident radiation of predetermined wavelength when the incident radiation passes through an area of the substrate where the optical nanostructures are located. The optical nanostructures overlie the grating coupler so that the incident radiation of predetermined wavelength crosses the optical die where the optical nanostructures are located before reaching the grating coupler.

Abstract: A semiconductor structure including a first die, a second die stacked on the first die, a smoothing layer disposed on the first die and a filling material layer disposed on the smoothing layer. The second die has a dielectric portion and a semiconductor material portion disposed on the dielectric portion. The smoothing layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is disposed on the first dielectric layer. The dielectric portion is surrounded by the smoothing layer, and the semiconductor material portion is surrounded by the filling material layer. A material of the first dielectric layer is different from a material of the second dielectric layer and a material of the filling material layer.

Abstract: A method includes bonding a top die to a bottom die, depositing a first dielectric liner on the top die, and depositing a gap-fill layer on the first dielectric liner. The gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon oxide. The method further includes etching the gap-fill layer and the first dielectric liner to form a through-opening, wherein a metal pad in the bottom die is exposed to the through-opening, depositing a second dielectric liner lining the through-opening, filling the through-opening with a conductive material to form a through-via connecting to the metal pad, and forming a redistribution structure over and electrically connecting to the top die and the through-via.

Abstract: A method includes: forming first bond pads along a wafer; bonding a first die to a first set of the first bond pads, the first die being electrically connected to the wafer; depositing a gap-fill dielectric over the wafer and around the first die; forming openings in the gap-fill dielectric; forming first active through vias in physical contact with the second set of the first bond pads and first dummy through vias in physical contact with the third set of the first bond pads, the first active through vias being electrically connected to the wafer, the first dummy through vias being electrically isolated from the wafer; forming second bond pads along the first die, the first active through vias, and the first dummy through vias; and bonding a second die to the first die and to a first active via of the first active through vias.

Abstract: A method includes bonding a top die to a bottom die, depositing a first dielectric liner on the top die, and depositing a gap-fill layer on the first dielectric liner. The gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon oxide. The method further includes etching the gap-fill layer and the first dielectric liner to form a through-opening, wherein a metal pad in the bottom die is exposed to the through-opening, depositing a second dielectric liner lining the through-opening, filling the through-opening with a conductive material to form a through-via connecting to the metal pad, and forming a redistribution structure over and electrically connecting to the top die and the through-via.

Abstract: A method includes bonding a top die to a bottom die, depositing a first dielectric liner on the top die, and depositing a gap-fill layer on the first dielectric liner. The gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon oxide. The method further includes etching the gap-fill layer and the first dielectric liner to form a through-opening, wherein a metal pad in the bottom die is exposed to the through-opening, depositing a second dielectric liner lining the through-opening, filling the through-opening with a conductive material to form a through-via connecting to the metal pad, and forming a redistribution structure over and electrically connecting to the top die and the through-via.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an interconnect structure disposed over a semiconductor substrate, contact pads disposed on the interconnect structure, a dielectric structure disposed on the interconnect structure and covering the contact pads, bonding connectors covered by the dielectric structure and landing on the contact pads, and a dummy feature covered by the dielectric structure and laterally interposed between adjacent two of the bonding connectors. Top surfaces of the bonding connectors are substantially coplanar with a top surface of the dielectric structure, and the bonding connectors are electrically coupled to the interconnect structure through the contact pads.

Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Abstract: A manufacturing method of a semiconductor structure includes: forming a liner structure on an inner sidewall of a dielectric layer overlying a semiconductor substrate; forming a via hole in an area of the semiconductor substrate which is exposed by the liner structure, wherein an overhang portion of the semiconductor substrate having a tapering arc-shaped profile and overhanging the via hole is formed; and filling the via hole with a conductive material.

Abstract: A manufacturing method of a through substrate via includes at least the following steps. A protective liner is formed within an opening of a dielectric layer, where the opening exposes a portion of a semiconductor substrate underlying the dielectric layer. The portion of the semiconductor substrate is removed through the opening, where an overhang portion is formed at a top edge of the semiconductor substrate and masked by the protective liner after the removing. The overhang portion of the semiconductor substrate, the protective liner, and a portion of the dielectric layer adjoining the protective liner is removed to form a via hole. A conductive material is formed in the via hole.

Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.

Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.

Abstract: A die bonding tool having a tool head including a plurality of openings fluidly coupled to a vacuum source to selectively secure a semiconductor die onto the tool head via the application of a suction force. The plurality of openings have non-uniform cross-sectional areas, including one or more first openings having a first cross-sectional area and one or more second openings having a second cross-sectional area that is greater than the first cross-section area. A first minimum offset distance between each of the first openings and any peripheral edge of the tool head is less than a second minimum offset distance between each of the second openings and any peripheral edge of the tool head. The configuration of the openings in the tool head may improve bonding of the semiconductor die to a substrate by inhibiting air becoming trapped between the semiconductor die and the substrate during the bonding process.