Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.

Abstract: A chip package includes a semiconductor substrate, an anti-reflection layer, and a metal multi-layer. The semiconductor substrate has an optical sensing area. The anti-reflection layer is located on the semiconductor substrate. The metal multi-layer is located on and in contact with the anti-reflection layer. The metal multi-layer includes a redistribution line and two probe pads. Two ends of the redistribution line respectively extend to the two probe pads. The redistribution line is located in the optical sensing area, and the two probe pads are located outside the optical sensing area. The orthographic projection area of the redistribution line in the optical sensing area is less than 1% of the area of the optical sensing area.

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

Abstract: A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.

Abstract: A chip package includes a semiconductor substrate, a light-transmissive plate, a bonding layer, and a light-shielding layer. The bonding layer is located between the semiconductor substrate and the light-transmissive plate. The semiconductor substrate, the bonding layer, and the light-transmissive plate jointly define a sidewall including a first region and a second region. The first region extends from the semiconductor substrate to the light-transmissive plate, and is recessed relative to the second region. The light-shielding layer covers the sidewall and includes an extending portion, a wide portion, and a narrow portion. The extending portion is located on a surface of the semiconductor substrate facing away from the bonding layer. The wide portion is located on the first region of the sidewall. The narrow portion is located on the second region of the sidewall.

Abstract: A circuit substrate in a chip package is provided. The circuit substrate includes first and second insulating layers covering opposite first and second surfaces of the semiconductor substrate, respectively. The circuit substrate also includes first and second pads disposed in the first and second insulating layers, respectively, and laterally separated from an opening that extends from the first surface to the second surface of the semiconductor substrate. The circuit substrate further includes first and second under bump metallization (UBM) layers disposed on the first and second pads, respectively. The first UBM layer has a surface protruding above the first insulating layer, and the second UBM layer extends from the second pad onto the second insulating layer, and is partially recessed into the second insulating layer to form a concave surface.

Abstract: A chip package includes an application chip, a micro-electromechanical systems (MEMS) chip, a conductive element, a bonding wire, and a molding compound. The application chip has a conductive pad. The MEMS chip is located on the application chip, and includes a main body and a cap. The main body is located between the cap and the application chip. The main body has a conductive pad. The conductive element is located on the conductive pad of the main body of the MEMS chip. The bonding wire extends from the conductive element to the conductive pad of the application chip. The molding compound is located on the application chip and surrounds the MEMS chip. The conductive element and the bonding wire are located in the molding compound.

Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.

Abstract: A chip package includes a carrier board, a chip, a light transmissive sheet, a supporting element, and a molding material. The chip is located on the carrier board and has a sensing area. The light transmissive sheet is located above the supporting element and covers the sensing area of the chip. The supporting element is located between the light transmissive sheet and the chip, and surrounds the sensing area of the chip. The molding material is located on the carrier board and surrounds the chip and the light transmissive sheet. A top surface of the molding material is lower than a top surface of the light transmissive sheet.

Abstract: A chip package includes a light transmissive sheet, a chip, a bonding layer, and an insulating layer. The light transmissive sheet has a protruding portion. A first surface of the chip faces toward the light transmissive sheet and has a sensing area. The bonding layer is located between the chip and the light transmissive sheet. The sum of a thickness of the chip and a thickness of the bonding layer is greater than or equal to a thickness of the light transmissive sheet. A protruding portion of the light transmissive sheet protrudes from a sidewall of the chip and a sidewall of the bonding layer. The insulating layer extends from a second surface of the chip to the protruding portion of the light transmissive sheet along the sidewall of the chip and the sidewall of the bonding layer.

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

Abstract: A chip package includes a sensing element, a dam layer, and a light transmissive cover. A surface of the sensing element has a sensing area and a conductive pad. The conductive pad is adjacent to an edge of the surface of the sensing element. The dam layer is located on the surface of the sensing element and surrounds the sensing area. The dam layer has a main portion and plural mark portions. The mark portions are respectively located in plural corners of the main portion, located in a sidewall of the main portion, respectively located on plural corners of the sensing element, respectively located on plural inner edges of the main portion, or respectively located on plural outer edges of the main portion. The light transmissive cover is located on the dam layer.

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.