Patents by Inventor Tsang-Yu Liu

Tsang-Yu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11319208
    Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: May 3, 2022
    Assignee: XINTEC INC.
    Inventors: Tsang-Yu Liu, Chaung-Lin Lai, Shu-Ming Chang
  • Patent number: 11310904
    Abstract: A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 19, 2022
    Assignee: XINTEC INC.
    Inventors: Tsang-Yu Liu, Po-Han Lee, Wei-Ming Chien
  • Publication number: 20210343591
    Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 4, 2021
    Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
  • Patent number: 11137559
    Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: October 5, 2021
    Assignee: XINTEC INC.
    Inventors: Jiun-Yen Lai, Yu-Ting Huang, Hsing-Lung Shen, Tsang-Yu Liu, Hui-Hsien Wu
  • Patent number: 11121031
    Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 14, 2021
    Assignee: XINTEC INC.
    Inventors: Chia-Sheng Lin, Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen
  • Publication number: 20210269303
    Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.
    Type: Application
    Filed: February 24, 2021
    Publication date: September 2, 2021
    Inventors: Wei-Luen SUEN, Jiun-Yen LAI, Hsing-Lung SHEN, Tsang-Yu LIU
  • Patent number: 11107759
    Abstract: A chip package includes a lower substrate, a first silicon nitride substrate, a bonding layer, an upper substrate, a first functional layer, a transparent conductive layer, an isolation layer, and a first conductive pad. The supporting layer is located between the lower substrate and the first silicon nitride substrate, and is made of a material including Benzocyclobutene (BCB). The upper substrate is located on the first silicon nitride substrate. The first functional layer is located between the upper substrate and the first silicon nitride substrate. The transparent conductive layer is located on the upper substrate. The isolation layer covers the upper substrate and the transparent conductive layer. The first conductive pad is located in the isolation layer and in electrical contact with the transparent conductive layer.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 31, 2021
    Assignee: XINTEC INC.
    Inventors: Wei-Luen Suen, Jiun-Yen Lai, Hsing-Lung Shen, Tsang-Yu Liu
  • Publication number: 20210104455
    Abstract: A chip package includes a lower substrate, a first silicon nitride substrate, a bonding layer, an upper substrate, a first functional layer, a transparent conductive layer, an isolation layer, and a first conductive pad. The supporting layer is located between the lower substrate and the first silicon nitride substrate, and is made of a material including Benzocyclobutene (BCB). The upper substrate is located on the first silicon nitride substrate. The first functional layer is located between the upper substrate and the first silicon nitride substrate. The transparent conductive layer is located on the upper substrate. The isolation layer covers the upper substrate and the transparent conductive layer. The first conductive pad is located in the isolation layer and in electrical contact with the transparent conductive layer.
    Type: Application
    Filed: September 29, 2020
    Publication date: April 8, 2021
    Inventors: Wei-Luen SUEN, Jiun-Yen LAI, Hsing-Lung SHEN, Tsang-Yu LIU
  • Patent number: 10950738
    Abstract: A chip package is provided. the chip package includes a substrate having an upper surface, a lower surface, and a sidewall surface that is at an edge of the substrate. The substrate includes a sensing device adjacent to the upper surface of the substrate to sense a light source. The chip package also includes a first color filter layer disposed on the upper surface of the substrate to shield the light source. The first color filter layer includes an opening, so that the first color filter layer surrounds the sensing device via the opening. In addition, the chip package includes a redistribution layer disposed on the lower surface of the substrate. A method of forming the chip package is also provided.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 16, 2021
    Assignee: XINTEC INC.
    Inventors: Shu-Ming Chang, Tsang-Yu Liu
  • Publication number: 20210066379
    Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.
    Type: Application
    Filed: November 17, 2020
    Publication date: March 4, 2021
    Inventors: Yen-Shih HO, Tsang-Yu LIU, Po-Han LEE
  • Publication number: 20210032096
    Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 4, 2021
    Inventors: Tsang-Yu LIU, Chaung-Lin LAI, Shu-Ming CHANG
  • Patent number: 10833118
    Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 10, 2020
    Assignee: XINTEC INC.
    Inventors: Tsang-Yu Liu, Chia-Ming Cheng
  • Publication number: 20200333542
    Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 22, 2020
    Inventors: Jiun-Yen LAI, Yu-Ting HUANG, Hsing-Lung SHEN, Tsang-Yu LIU, Hui-Hsien WU
  • Publication number: 20200144116
    Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 7, 2020
    Inventors: Chia-Sheng LIN, Hui-Hsien WU, Jian-Hong CHEN, Tsang-Yu LIU, Kuei-Wei CHEN
  • Publication number: 20200137879
    Abstract: A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 30, 2020
    Inventors: Tsang-Yu LIU, Po-Han LEE, Wei-Ming CHIEN
  • Publication number: 20200044099
    Abstract: A chip package is provided. the chip package includes a substrate having an upper surface, a lower surface, and a sidewall surface that is at an edge of the substrate. The substrate includes a sensing device adjacent to the upper surface of the substrate to sense a light source. The chip package also includes a first color filter layer disposed on the upper surface of the substrate to shield the light source. The first color filter layer includes an opening, so that the first color filter layer surrounds the sensing device via the opening. In addition, the chip package includes a redistribution layer disposed on the lower surface of the substrate. A method of forming the chip package is also provided.
    Type: Application
    Filed: July 15, 2019
    Publication date: February 6, 2020
    Inventors: Shu-Ming CHANG, Tsang-Yu LIU
  • Patent number: 10461117
    Abstract: A method for manufacturing a semiconductor structure includes the following steps. A first carrier is adhered to a first surface of a wafer by a first temporary bonding layer. A second surface of the wafer facing away from the first carrier is etched to form at least one through hole and at least one trench, in which a conductive pad of the wafer is exposed through the through hole. An isolation layer is formed on the second surface of the wafer, a sidewall of the through hole, and a sidewall of the trench. A second carrier is adhered to the second surface of the wafer by a second temporary bonding layer, and thus the through hole and the trench are covered by the second carrier. The first carrier and the first temporary bonding layer are removed.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 29, 2019
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Tsang-Yu Liu, Chia-Sheng Lin, Chaung-Lin Lai
  • Patent number: 10318784
    Abstract: This invention provides a touch panel-sensing chip package module complex, comprising: a touch panel with a first top surface and a first bottom surface opposite to each other, wherein the first bottom surface having a first cavity with a bottom wall surrounded by a sidewall; a color layer formed on the bottom wall and the first bottom surface adjacent to the cavity; and a chip scale sensing chip package module bonded to the cavity by the color layer formed on the bottom wall of the cavity.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 11, 2019
    Assignee: XINTEC INC.
    Inventors: Shu-Ming Chang, Tsang-Yu Liu, Yen-Shih Ho
  • Publication number: 20180358398
    Abstract: A chip package includes a chip, an isolation layer, a redistribution layer, a passivation layer, and an encapsulation layer. The chip has a sensor, a conductive pad, a through hole, a top surface, and a bottom surface that is opposite the top surface. The sensor and the conductive pad are located on the top surface, and the conductive pad is in the through hole. The isolation layer is located on the bottom surface of the chip and a sidewall that surrounds the through hole. The redistribution layer is located on the isolation layer, and is in electrical contact with the conductive pad. The passivation layer is located on the isolation layer and the redistribution layer. The encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad, and has a flat surface facing away from the chip.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 13, 2018
    Inventors: Yen-Shih HO, Tsang-Yu LIU, Po-Han LEE
  • Patent number: 10152180
    Abstract: This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to each other, a touch plate having a second top surface and a second bottom surface opposite to each other, formed above the sensing chip, and a color layer, sandwiched between the sensing chip and the touch plate, wherein the sensing chip comprises a sensing device formed nearby the first top surface and a plurality of conductive pads formed nearby the first top surface and adjacent to the sensing device, a plurality of through silicon vias exposing their corresponding conductive pads formed on the first bottom surface, a plurality of conductive structures formed on the first bottom surface, and a re-distribution layer overlaying the first bottom surface and each through silicon via to electrically connect each conductive pad and each conductive structure.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: December 11, 2018
    Assignee: XINTEC INC.
    Inventors: Shu-Ming Chang, Yu-Lung Huang, Tsang-Yu Liu, Yen-Shih Ho