Patents by Inventor Tsang-Yu Liu

Tsang-Yu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150295097
    Abstract: A chip package includes semiconductor chips, inner spacers, cavities, conductive portions and solder balls. The semiconductor chip has at least an electronic component and at least an electrically conductive pad disposed on an upper surface thereof. The conductive pad is arranged abreast to one side of the electronic component and electrically connected thereto. The cavities open to a lower surface of the semiconductor chip and extend toward the upper surface to expose the conductive pad on the upper surface. The conductive portions fill the cavities from the lower surface and electrically connected the to conductive pad. The solder balls are disposed on the lower surface and electrically connected to the conductive portions. A gap is created between an outer wall of the inner spacers and an edge of the semiconductor chip.
    Type: Application
    Filed: April 9, 2015
    Publication date: October 15, 2015
    Inventors: Tsang-Yu LIU, Shu-Ming CHANG, Po-Han LEE
  • Publication number: 20150287619
    Abstract: An embodiment of this invention provides a separation apparatus for separating a stacked article, such as a semiconductor chip package with sensing functions, comprising a substrate and a cap layer formed on the substrate. The separation apparatus comprises a vacuum nozzle head including a suction pad having a top surface and a bottom surface, a through hole penetrating the top surface and the bottom surface of the suction pad, and a hollow vacuum pipe connecting the through hole to a vacuum pump; a stage positing under the vacuum nozzle head and substantially aligning with the suction pad; a control means coupling to the vacuum nozzle head to lift upward or lower down the vacuum nozzle head; and a first cutter comprising a first cutting body and a first knife connecting to the first cutting body.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 8, 2015
    Inventors: Yen-Shih HO, Tsang-Yu LIU, Chia-Sheng LIN, Yi-Ming CHANG
  • Publication number: 20150284244
    Abstract: A method for forming a chip package is provided. The method includes providing a substrate and a capping layer, wherein the substrate has a sensing device therein adjacent to a surface of the substrate. The capping layer is attached to the surface of the substrate by an adhesive layer, wherein the adhesive layer covers the sensing device. A dicing process is performed on the substrate, the adhesive layer, and the capping layer along a direction to form individual chip packages.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 8, 2015
    Inventors: Yen-Shih HO, Tsang-Yu LIU, Chia-Sheng LIN, Yi-Ming CHANG
  • Patent number: 9153528
    Abstract: Embodiments of the present invention provide a chip package including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: October 6, 2015
    Assignee: XINTEC INC.
    Inventors: Po-Shen Lin, Tsang-Yu Liu, Yen-Shih Ho, Chih-Wei Ho, Yu-Min Liang
  • Patent number: 9153707
    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: October 6, 2015
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Ying-Nan Wen, Tsang-Yu Liu
  • Publication number: 20150279808
    Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 1, 2015
    Inventors: Chia-Lun SHEN, Yi-Ming CHANG, Tsang-Yu LIU, Yen-Shih HO
  • Patent number: 9142486
    Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: September 22, 2015
    Inventors: Tsang-Yu Liu, Yi-Ming Chang, Tzu-Min Chen
  • Patent number: 9136241
    Abstract: An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: September 15, 2015
    Inventors: Yu-Lin Yen, Kuo-Hua Liu, Yu-Lung Huang, Tsang-Yu Liu, Yen-Shih Ho
  • Publication number: 20150228557
    Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess. A method for forming the chip package is also provided.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 13, 2015
    Inventors: Chia-Ming CHENG, Tsang-Yu LIU, Chi-Chang LIAO, Yu-Lung HUANG
  • Publication number: 20150228536
    Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.
    Type: Application
    Filed: February 10, 2015
    Publication date: August 13, 2015
    Inventors: Yen-Shih HO, Tsang-Yu LIU, Chia-Sheng LIN, Chia-Ming CHENG, Shu-Ming CHANG, Tzu-Wen TSENG
  • Publication number: 20150206916
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A redistribution layer, an insulating layer, and a conductive structure are formed on a second surface of the wafer opposite to the first surface, such that a semiconductor element is formed. The semiconductor element is diced from the insulating layer to the carrier, such that the semiconductor element forms at least one sub-semiconductor element. UV light is used to irradiate the sub-semiconductor element, such that adhesion of the temporary bonding layer is eliminated. The carrier of the sub-semiconductor element is removed.
    Type: Application
    Filed: January 13, 2015
    Publication date: July 23, 2015
    Inventors: Po-Han LEE, Shu-Ming CHANG, Tsang-Yu LIU, Yen-Shih HO, Chien-Hung LIU
  • Publication number: 20150179831
    Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 25, 2015
    Inventors: Wei-Luen SUEN, Wei-Ming CHIEN, Po-Han LEE, Tsang-Yu LIU, Yen-Shih HO
  • Publication number: 20150162245
    Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.
    Type: Application
    Filed: January 13, 2015
    Publication date: June 11, 2015
    Inventors: Bing-Siang CHEN, Chien-Hui CHEN, Shu-Ming CHANG, Tsang-Yu LIU, Yen-Shih HO
  • Patent number: 9054114
    Abstract: An embodiment of the present invention provides a manufacturing method of a chip package structure including: providing a first substrate having a plurality of predetermined scribe lines defined thereon, wherein the predetermined scribe lines define a plurality of device regions; bonding a second substrate to the first substrate, wherein a spacing layer is disposed therebetween and has a plurality of chip support rings located in the device regions respectively and a cutting support structure located on peripheries of the chip support rings, and the spacing layer has a gap pattern separating the cutting support structure from the chip support rings; and cutting the first substrate and the second substrate to form a plurality of chip packages. Another embodiment of the present invention provides a chip package structure.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: June 9, 2015
    Assignee: XINTEC INC.
    Inventors: Hung-Jen Lee, Shu-Ming Chang, Chen-Han Chiang, Tsang-Yu Liu, Yen-Shih Ho
  • Publication number: 20150123231
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 7, 2015
    Inventors: Wei-Ming CHIEN, Po-Han LEE, Tsang-Yu LIU, Yen-Shih HO
  • Patent number: 9024437
    Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: May 5, 2015
    Inventors: Yu-Lin Yen, Chien-Hui Chen, Tsang-Yu Liu, Yen-Shih Ho
  • Patent number: 9018770
    Abstract: A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 28, 2015
    Assignee: Xintec Inc.
    Inventors: Tsang-Yu Liu, Chia-Ming Cheng
  • Patent number: 9006896
    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure located in the dielectric layer and electrically connected to the device region, wherein the conducting pad structure comprises a stacked structure of a plurality of conducting pad layers; a support layer disposed on a top surface of the conducting pad structure; and a protection layer disposed on the second surface of the semiconductor substrate.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: April 14, 2015
    Assignee: Xintec Inc.
    Inventors: Yu-Lung Huang, Tsang-Yu Liu, Shu-Ming Chang
  • Publication number: 20150099357
    Abstract: A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 9, 2015
    Inventors: Chuan-Jin SHIU, Tsang-Yu LIU, Chih-Wei HO, Shih-Hsing CHAN, Ching-Jui CHUANG
  • Publication number: 20150097286
    Abstract: A chip package includes a packaging substrate, a semiconductor chip, and a plurality of conductive structures. The semiconductor chip has a central region and an edge region that surrounds the central region. The conductive structures are between the packaging substrate and the semiconductor chip. The conductive structures have different heights, and the heights of the conductive structures are gradually increased from the central region of the semiconductor chip to the edge region of the semiconductor chip, such that a distance between the edge region of the semiconductor chip and the packaging substrate is greater than a distance between the central region of the semiconductor chip and the packaging substrate.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 9, 2015
    Inventors: Wei-Luen SUEN, Chia-Sheng LIN, Yen-Shih HO, Tsang-Yu LIU