Abstract: A detector includes a frequency multiplier and a transceiving node. The frequency multiplier includes a first terminal, a second terminal and an output terminal. The first terminal is used to receive a first injection signal having a first frequency. The output terminal is used to output an output signal. The second terminal is used to receive a second injection signal having a second frequency. The frequency multiplier is used to output the output signal at a frequency substantially equal to a multiple of the first frequency by injection locking and pull the output signal to the second frequency by injection pulling. The transceiving node is coupled to the output terminal and the second terminal of the frequency multiplier. The transceiving node is used to transmit the output signal, and receive a received signal having a third frequency. The received signal is used to update the second injection signal.

Abstract: A subsampling motion detector configured to detect motion information of an object under measurement receives a first wireless radio frequency (RF) signal and transmits a second wireless RF signal, the first wireless RF signal being generated by reflecting the second wireless RF signal from the object. The subsampling motion detector includes a controllable oscillator outputting an oscillation signal, wherein the first wireless RF signal is injected to the controllable oscillator for controlling the controllable oscillator through injecting locking.

Abstract: A detector includes a frequency multiplier and a transceiving node. The frequency multiplier includes a first terminal, a second terminal and an output terminal. The first terminal is used to receive a first injection signal having a first frequency. The output terminal is used to output an output signal. The second terminal is used to receive a second injection signal having a second frequency. The frequency multiplier is used to output the output signal at a frequency substantially equal to a multiple of the first frequency by injection locking and pull the output signal to the second frequency by injection pulling. The transceiving node is coupled to the output terminal and the second terminal of the frequency multiplier. The transceiving node is used to transmit the output signal, and receive a received signal having a third frequency. The received signal is used to update the second injection signal.

Abstract: A detector includes an oscillation source, a frequency multiplier, a transceiver and a demodulator. The oscillation source generates a first injection signal with a first frequency. The frequency multiplier receives the first injection signal, outputs an output signal and receives a second injection signal with a second frequency. The frequency multiplier uses injection locking to lock a frequency of the output signal at a multiple of the first frequency, and uses injection pulling to pull the frequency of the output signal to the second frequency. The transceiver transmits the output signal and receives a received signal with a third frequency for updating the second injection signal. The demodulator performs a demodulation operation according to the output signal so as to generate a displacement signal.

Abstract: A detector includes an oscillation source, a frequency multiplier, a transceiver and a demodulator. The oscillation source generates a first injection signal with a first frequency. The frequency multiplier receives the first injection signal, outputs an output signal and receives a second injection signal with a second frequency. The frequency multiplier uses injection locking to lock a frequency of the output signal at a multiple of the first frequency, and uses injection pulling to pull the frequency of the output signal to the second frequency. The transceiver transmits the output signal and receives a received signal with a third frequency for updating the second injection signal. The demodulator performs a demodulation operation according to the output signal so as to generate a displacement signal.

Abstract: A projection apparatus is provided. The projection apparatus includes a light-emitting unit array, an optical sensor, and a control unit. The light-emitting unit array is for emitting an image beam. The optical sensor is for detecting electromagnetic waves so as to generate a signal. The control unit is electrically coupled to the light-emitting unit array and the optical sensor for controlling emission of the light-emitting unit array according to the signal from the optical sensor.

Abstract: An asynchronous FIFO interface having a readout clock asynchronous with a write clock is provided. The asynchronous FIFO interface includes a FIFO buffer, a clock controller, a reference source and a signal source. The FIFO buffer receives a digital signal from an ADC according to the write clock and outputs a digital signal to a processor according to the readout clock. The clock controller outputs a clock control signal according to the amount of data stored in the FIFO buffer. The reference source provides an oscillation frequency. The signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the readout clock by a second integer divisor to generate an input frequency, and outputs a control signal by comparing the reference frequency with the input frequency.

Abstract: A light emitting device includes a plurality of micro diodes, which are electrically connected to constitute a bridge rectifier circuit. Each branch of the bridge rectifier circuit includes a single micro diode or a plurality of micro diodes. The light emitting device is electrically connected to an AC power source, which alternately drives the light emitting device in two current loops. Therefore, the micro diodes in two current loops of the bridge rectifier circuit emit light by turns.

Abstract: A digital phase-locked loop having a phase frequency detector (PFD), a 3-state phase frequency detection converter (3-state PFD converter), a loop filter and a digital voltage-controlled oscillator is provided. The PFD receives an input frequency and a reference frequency and outputs a first signal and a second signal based on the phase difference between the input frequency and the reference frequency. The 3-state PFD converter outputs a 3-state signal according to the first and second signals, wherein the 3-state signal is presented in 1, 0 and ?1. The loop filter outputs at least one control bit based on only the 3-state signal. The DCO adjusts the outputted oscillation frequency according to the control bit.

Abstract: A circuit device includes an option pad, a first power source pad, and a first ground pad, wherein the option pad, the first power source pad, and the first ground pad are formed over various portions of a top surface of the circuit device, and a function of the circuit device is determined by coupling the option pad with one of the first power source pad and the first ground pad through a wire bond.

Abstract: A projection apparatus is provided. The projection apparatus includes a light-emitting unit array, an optical sensor, and a control unit. The light-emitting unit array is for emitting an image beam. The optical sensor is for detecting electromagnetic waves so as to generate a signal. The control unit is electrically coupled to the light-emitting unit array and the optical sensor for controlling emission of the light-emitting unit array according to the signal from the optical sensor.

Abstract: A light-emitting unit array includes a plurality of light-emitting units arranged and integrated monolithically in an array, and each of the light-emitting units includes a first doped type layer, a second doped type layer, a light-emission layer, and a photonic crystal structure. The light emission layer is disposed between the first doped type layer and the second doped type layer, wherein the second doped type layer has a surface facing away from the light emission layer. The photonic crystal structure is disposed on the surface of the second doped type layer.

Abstract: The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous. The asynchronous FIFO interface comprises a FIFO buffer, a clock controller and a variable integer divider. The FIFO buffer inputs at least one data with the write-in clock, and outputs the at least one data with the read-out clock. The clock controller outputs a clock control signal according to a number of data stored in the FIFO buffer. The variable integer divider divides a first signal to generate the read-out clock or the write-in clock by an integer divisor controlled by the clock control signal in order to adjust the number of data stored in the FIFO buffer.

Abstract: An asynchronous FIFO interface having a readout clock asynchronous with a write clock is provided. The asynchronous FIFO interface includes a FIFO buffer, a clock controller, a reference source and a signal source. The FIFO buffer receives a digital signal from an ADC according to the write clock and outputs a digital signal to a processor according to the readout clock. The clock controller outputs a clock control signal according to the amount of data stored in the FIFO buffer. The reference source provides an oscillation frequency. The signal source divides the oscillation frequency by a first integer divisor to generate a reference frequency, divides the readout clock by a second integer divisor to generate an input frequency, and outputs a control signal by comparing the reference frequency with the input frequency.

Abstract: A digital phase-locked loop having a phase frequency detector (PFD), a 3-state phase frequency detection converter (3-state PFD converter), a loop filter and a digital voltage-controlled oscillator is provided. The PFD receives an input frequency and a reference frequency and outputs a first signal and a second signal based on the phase difference between the input frequency and the reference frequency. The 3-state PFD converter outputs a 3-state signal according to the first and second signals, wherein the 3-state signal is presented in 1, 0 and ?1. The loop filter outputs at least one control bit based on only the 3-state signal. The DCO adjusts the outputted oscillation frequency according to the control bit.

Abstract: A projection display chip comprises a micro light emitting array comprising a plurality of micro LEDs, a micro collimation array comprising a plurality of micro collimation devices, and a projection micro lens array comprising a plurality of micro lenses. Each micro LED has a corresponding driving circuit device. The plurality of micro lenses has different optical axes to enlarge projected images.

Abstract: A light emitting device includes a plurality of micro diodes, which are electrically connected to constitute a bridge rectifier circuit. Each branch of the bridge rectifier circuit includes a single micro diode or a plurality of micro diodes. The light emitting device is electrically connected to an AC power source, which alternately drives the light emitting device in two current loops. Therefore, the micro diodes in two current loops of the bridge rectifier circuit emit light by turns.

Abstract: An adjustable digital lock detector for a phase-locked loop (PLL) has a variable counter for outputting an output signal corresponding to a first clock signal, a target count number signal, and a count number offset signal, a latch for sampling the output signal of the variable counter and outputting a latch output signal according to a result of sampling the output signal, a lead/lag detector for receiving the latch output signal and outputting the count number offset signal according to a predetermined state of the latch output signal, and an arbiter for receiving the latch output signal and outputting an arbiter output signal according to the latch output signal and a second clock signal.

Abstract: An adjustable digital lock detector for a phase-locked loop (PLL) has a variable counter for outputting an output signal corresponding to a first clock signal, a target count number signal, and a count number offset signal, a latch for sampling the output signal of the variable counter and outputting a latch output signal according to a result of sampling the output signal, a lead/lag detector for receiving the latch output signal and outputting the count number offset signal according to a predetermined state of the latch output signal, and an arbiter for receiving the latch output signal and outputting an arbiter output signal according to the latch output signal and a second clock signal.

Abstract: The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous. The asynchronous FIFO interface comprises a FIFO buffer, a clock controller and a variable integer divider. The FIFO buffer inputs at least one data with the write-in clock, and outputs the at least one data with the read-out clock. The clock controller outputs a clock control signal according to a number of data stored in the FIFO buffer. The variable integer divider divides a first signal to generate the read-out clock or the write-in clock by an integer divisor controlled by the clock control signal in order to adjust the number of data stored in the FIFO buffer.