Abstract: Provided is a composite electrode material. The composite electrode material is disposed on a surface of an electrode. The composite electrode material includes a plurality of conductive material layers and a plurality of active material layers. The conductive material layers and the active material layers are alternately stacked along a direction non-parallel to the surface of the electrode, and are arranged disorderly along a direction parallel to the surface of the electrode.

Abstract: A conductive-bridging random access memory and a method for fabricating a conductive-bridging random access memory are provided. The conductive-bridging random access memory includes a bottom electrode layer on a semiconductor substrate, an electrical resistance switching layer on the bottom electrode layer, an electron-capturing layer on the electrical resistance switching layer, a barrier layer on the electron-capturing layer, an ion source layer on the barrier layer, and a top electrode layer on the ion source layer. The electron-capturing layer includes electron-capturing material, and the electron affinity of the electron-capturing material is at least 60 KJ/mole.

Abstract: A conductive-bridging random access memory is provided. The conductive-bridging random access memory includes a bottom electrode layer on a semiconductor substrate, an electrical resistance switching layer on the bottom electrode layer, a barrier layer on the electrical resistance switching layer, a top electrode layer on the barrier layer, and a high thermal-conductive material layer between the bottom electrode layer and the barrier layer. The high thermal-conductive material layer has a thermal conductivity in a range of 70-5000 W/mK.

Abstract: A conductive-bridging random access memory and a method for fabricating a conductive-bridging random access memory are provided. The conductive-bridging random access memory includes a bottom electrode layer on a semiconductor substrate, an electrical resistance switching layer on the bottom electrode layer, an electron-capturing layer on the electrical resistance switching layer, a barrier layer on the electron-capturing layer, an ion source layer on the barrier layer, and a top electrode layer on the ion source layer. The electron-capturing layer includes electron-capturing material, and the electron affinity of the electron-capturing material is at least 60 KJ/mole.

Abstract: Provided is a composite electrode material. The composite electrode material is disposed on a surface of an electrode. The composite electrode material includes a plurality of conductive material layers and a plurality of active material layers. The conductive material layers and the active material layers are alternately stacked along a direction non-parallel to the surface of the electrode, and are arranged disorderly along a direction parallel to the surface of the electrode.

Abstract: Provided is a manufacturing method of a composite electrode material which includes the following steps. An electro-deposition device is provided. The electro-deposition device includes a mixed solution and a working electrode and an auxiliary electrode placed in the mixed solution. The mixed solution includes a conductive material precursor and an active material precursor. An alternating voltage is applied to the electro-deposition device, so as to perform a plurality of electrochemical reactions on a surface of the auxiliary electrode and therefore to form a composite electrode material.

Abstract: A conductive-bridging random access memory is provided. The conductive-bridging random access memory includes a bottom electrode layer on a semiconductor substrate, an electrical resistance switching layer on the bottom electrode layer, a barrier layer on the electrical resistance switching layer, a top electrode layer on the barrier layer, and a high thermal-conductive material layer between the bottom electrode layer and the barrier layer. The high thermal-conductive material layer has a thermal conductivity in a range of 70-5000 W/mK.

Abstract: A high energy density asymmetric pseudocapacitor includes a cathode plate, an anode plate, and a separator. The cathode plate includes a first conductive substrate and a porous cathode film formed on the first conductive substrate. The porous cathode film includes a carbon nano-tube network and a plurality of composite flakes. Each of the composite flakes contains graphene, a transition metal compound and carbon nano-tubes. The anode plate includes a second conductive substrate and an anode film formed on the second conductive substrate. The anode film contains graphene and carbon nano-tubes.

Abstract: A resistive random access memory (RRAM) including a substrate, a conductive layer, a resistive switching layer, a copper-containing oxide layer, and an electron supply layer is provided. The conductive layer is disposed on the substrate. The resistive switching layer is disposed on the conductive layer. The copper-containing oxide layer is disposed on the resistive switching layer. The electron supply layer is disposed on the copper-containing oxide layer.

Abstract: A high energy density asymmetric pseudocapacitor includes a cathode plate, an anode plate, and a separator. The cathode plate includes a first conductive substrate and a porous cathode film formed on the first conductive substrate. The porous cathode film includes a carbon nano-tube network and a plurality of composite flakes. Each of the composite flakes contains graphene, a transition metal compound and carbon nano-tubes. The anode plate includes a second conductive substrate and an anode film formed on the second conductive substrate. The anode film contains graphene and carbon nano-tubes.

Abstract: A method of fabricating a memory cell includes forming a bottom electrode on a substrate, a variable resistive material layer on the bottom electrode, and a top electrode on the variable resistive material layer. A first metal oxide layer interposes the top electrode and the variable resistive material layer. In an embodiment, the first metal oxide layer is a self-formed layer provided by the oxidation of a portion of the top electrode. In an embodiment, a second metal oxide layer is provided interposing the first metal oxide layer and the variable resistive material layer. The second metal oxide may be a self-formed layer formed by the reduction of the variable resistive material layer.

Abstract: An exemplary embodiment of a non-volatile memory includes a bottom conductive layer, a resistive switching layer, an oxygen vacancy barrier layer and an upper conductive layer. The resistive switching layer is disposed on the bottom conductive layer. The oxygen vacancy barrier layer is disposed on the resistive switching layer. The upper conductive layer is disposed on the oxygen vacancy barrier layer.

Abstract: A method for fabricating a resistor for a resistance random access memory (RRAM) includes: (a) forming a first electrode over a substrate; (b) forming a variable resistance layer of zirconium oxide on the first electrode under a working temperature, which ranges from 175° C. to 225° C.; and (c) forming a second electrode of Ti on the variable resistance layer.

Abstract: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.

Abstract: An exemplary embodiment of a non-volatile memory includes a bottom conductive layer, a resistive switching layer, an oxygen vacancy barrier layer and an upper conductive layer. The resistive switching layer is disposed on the bottom conductive layer. The oxygen vacancy barrier layer is disposed on the resistive switching layer. The upper conductive layer is disposed on the oxygen vacancy barrier layer.

Abstract: A method of fabricating a memory cell includes forming a bottom electrode on a substrate, a variable resistive material layer on the bottom electrode, and a top electrode on the variable resistive material layer. A first metal oxide layer interposes the top electrode and the variable resistive material layer. In an embodiment, the first metal oxide layer is a self-formed layer provided by the oxidation of a portion of the top electrode. In an embodiment, a second metal oxide layer is provided interposing the first metal oxide layer and the variable resistive material layer. The second metal oxide may be a self-formed layer formed by the reduction of the variable resistive material layer.

Abstract: The present disclosure provides a memory cell. The memory cell includes a first electrode, a variable resistive material layer coupled to the first electrode, a metal oxide layer coupled the variable resistive material layer; and a second electrode coupled to the metal oxide layer. In an embodiment, the metal oxide layer provides a constant resistance.

Abstract: A method for fabricating a resistor for a resistance random access memory (RRAM) includes: (a) forming a first electrode over a substrate; (b) forming a variable resistance layer of zirconium oxide on the first electrode under a working temperature, which ranges from 175° C. to 225° C.; and (c) forming a second electrode of Ti on the variable resistance layer.

Abstract: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.

Abstract: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.