Abstract: This invention relates to a process for fabricating ZnO nanowires with high aspect ratio at low temperature, which is associated with semiconductor manufacturing process and a gate controlled field emission triode is obtained. The process comprises providing a semiconductor substrate, depositing a dielectric layer and a conducting layer, respectively, on the semiconductor substrate, defining the positions of emitter arrays on the dielectric layer and conducting layer, depositing an ultra thin ZnO film as a seeding layer on the substrate, growing the ZnO nanowires as the emitter arrays by using hydrothermal process, and etching the areas excluding the emitter arrays, then obtaining the gate controlled field emission triode.

Abstract: This invention relates to a process for fabricating ZnO nanowires with high aspect ratio at low temperature, which is associated with semiconductor manufacturing process and a gate controlled field emission triode is obtained. The process comprises providing a semiconductor substrate, depositing a dielectric layer and a conducting layer, respectively, on the semiconductor substrate, defining the positions of emitter arrays on the dielectric layer and conducting layer, depositing an ultra thin ZnO film as a seeding layer on the substrate, growing the ZnO nanowires as the emitter arrays by using hydrothermal process, and etching the areas excluding the emitter arrays, then obtaining the gate controlled field emission triode.

Abstract: The present disclosure provides a memory cell. The memory cell includes a first electrode, a variable resistive material layer coupled to the first electrode, a metal oxide layer coupled the variable resistive material layer; and a second electrode coupled to the metal oxide layer. In an embodiment, the metal oxide layer provides a constant resistance.

Abstract: A method for non-volatile memory fabrication is provided, in which a substrate is provided, a bottom electrode is formed on the substrate, a solution with precursors of Zr and Sr is coated on the bottom electrode, the solution on the bottom electrode surface is dried and then fired to form a resistor layer of SrZrO3, and a top electrode is formed on the resistor layer.

Abstract: A nonvolatile memory and a fabrication method thereof. The nonvolatile memory includes a substrate, a bottom electrode deposited on the substrate, a resistor layer deposited on the bottom electrode, and a top electrode on the resistor layer. The bottom electrode includes LaNiO3 and the resistor layer includes doped SrZrO3.

Abstract: This invention relates to a process for fabricating ZnO nanowires with high aspect ratio at low temperature, which is associated with semiconductor manufacturing process and a gate controlled field emission triode is obtained. The process comprises providing a semiconductor substrate, depositing a dielectric layer and a conducting layer, respectively, on the semiconductor substrate, defining the positions of emitter arrays on the dielectric layer and conducting layer, depositing an ultra thin ZnO film as a seeding layer on the substrate, growing the ZnO nanowires as the emitter arrays by using hydrothermal process, and etching the areas excluding the emitter arrays, then obtaining the gate controlled field emission triode.

Abstract: A method for non-volatile memory fabrication is provided, in which a substrate is provided, a bottom electrode is formed on the substrate, a solution with precursors of Zr and Sr is coated on the bottom electrode, the solution on the bottom electrode surface is dried and then fired to form a resistor layer of SrZrO3, and a top electrode is formed on the resistor layer.

Abstract: A nonvolatile memory and a fabrication method thereof. The nonvolatile memory includes a substrate, a bottom electrode deposited on the substrate, a resistor layer deposited on the bottom electrode, and a top electrode on the resistor layer. The bottom electrode includes LaNiO3 and the resistor layer includes doped SrZrO3.

Abstract: A ferroelectric memory structure is disclosed. The ferroelectric memory structure includes a substrate, an insulating layer formed on the substrate, a plurality of oxide electrodes formed on the insulating layer, a ferroelectric layer formed on the insulating layer and the plurality of oxide electrodes, and a plurality of metallic electrodes formed on the ferroelectric layer and corresponding to the plurality of the oxide electrodes.

Abstract: A ferroelectric memory structure is disclosed. The ferroelectric memory structure includes a substrate, an insulating layer formed on the substrate, a plurality of oxide electrodes formed on the insulating layer, a ferroelectric layer formed on the insulating layer and the plurality of oxide electrodes, and a plurality of metallic electrodes formed on the ferroelectric layer and corresponding to the plurality of the oxide electrodes.

Abstract: A novel SBTN (SraBibTacNbdOx) thin film which exhibits satisfactory ferroelectric properties is disclosed, wherein a lies between 0.5 and 1, b lies between 2 and 2.7, c lies between 1 and 1.4, d lies between 0.6 and 1.1, and x lies between 8 and 10. The composition of Sr0.8Bi2.5Ta1.2Nb0.9Ox wherein x lies between 9 and 10 is preferred. The Sr0.8Bi2.5Ta1.2Nb0.9Ox thin film is formed by two-target off-axis RF magnetron sputtering at a temperature down to about 600° C. One target is formed of Sr0.8Bi2.2Ta1.2Nb0.8O9, and the other target is formed of Bi2O3.

Abstract: A ceramic composition on the basis of a doped BaTiO.sub.3, a ceramic multilayer having such ceramic composition and a monolithic capacitor having such a composition are provided according to the invention. The composition corresponds to the formula(Ba.sub.1-a-b Ca.sub.a Dy.sub.b)(Ti.sub.1-c-d-e-f Zr.sub.c Mn.sub.d Nb.sub.e).sub.f O.sub.3+.delta.wherein: 0.00<a.ltoreq.0.200.006.ltoreq.b.ltoreq.0.0160.00<c.ltoreq.0.250.3b+0.7e<d.ltoreq.0.0140.001.ltoreq.e.ltoreq.0.0051.000<f.ltoreq.1.007.Capacitors having this ceramic composition as a dielectric material show an increased life-time well as a good resistance against degradation of their electrical properties if used at high temperatures under dc conditions.