Abstract: The invention provides a package structure of optical transceiver component, comprising: a metal base; a plurality of pins, at least one optical emitting diode and/or at least one optical receiving diode; wherein the pins are provided and passed through the metal base and insulated with the metal base by using an insulating material; the optical emitting diode and the optical receiving diode are each mounted on the metal base through a sub-mount, respectively. The optical emitting diode/optical receiving diode is connected to the pins neighboring therewith by a wire directly or through the sub-mount, when set the top surface of the pins be a reference level, at least one of the top surfaces of the optical emitting diode, the optical receiving diode, and sub-mount is flush with the reference level.

Abstract: The invention provides a package structure of optical transceiver component, comprising: a metal base; a plurality of pins, at least one optical emitting diode and/or at least one optical receiving diode; wherein the pins are provided and passed through the metal base and insulated with the metal base by using an insulating material; the optical emitting diode and the optical receiving diode are each mounted on the metal base through a sub-mount, respectively. The optical emitting diode/optical receiving diode is connected to the pins neighboring therewith by a wire directly or through the sub-mount, when set the top surface of the pins be a reference level, at least one of the top surfaces of the optical emitting diode, the optical receiving diode, and sub-mount is flush with the reference level.

Abstract: The present invention provides an optical transceiver module, comprising: a circuit substrate; a z-axis positioning base connected to the circuit substrate that, wherein the z-axis positioning base comprises two first sides respectively provided on two lateral sides of the optical transceiver sub-module, a second side provided between and connecting the two first sides, an opening corresponding in position to a side of the optical transceiver sub-module that faces away from the second side, and a step difference provided on each of the two first sides and the second side; a fiber-optic lens element provided on the z-axis positioning base and comprises a cover and a fiber-optic lens sub-module, wherein the cover comprises a recess and step differences surrounding the recess and respectively corresponding in position to the step differences provided on the z-axis positioning base, so as for the cover to be fitted on the z-axis positioning base.

Abstract: The present invention provides an optical transceiver module, comprising: a circuit substrate; a z-axis positioning base connected to the circuit substrate that, wherein the z-axis positioning base comprises two first sides respectively provided on two lateral sides of the optical transceiver sub-module, a second side provided between and connecting the two first sides, an opening corresponding in position to a side of the optical transceiver sub-module that faces away from the second side, and a step difference provided on each of the two first sides and the second side; a fiber-optic lens element provided on the z-axis positioning base and comprises a cover and a fiber-optic lens sub-module, wherein the cover comprises a recess and step differences surrounding the recess and respectively corresponding in position to the step differences provided on the z-axis positioning base, so as for the cover to be fitted on the z-axis positioning base.

Abstract: A BGA package structure and a method for fabricating the same, wherein the BGA package structure comprises: a substrate having a first surface used to carry a chip and a second surface opposite to the first surface, wherein the substrate is divided into several regions according to different distances from a central point of the substrate; a plurality of contact bonding pads on the second surface electrically connected with the chip; and a plurality of bumps respectively attached to each of the contact bonding pads, wherein the contact bonding pads and bumps in a region which is closest to the central point are the smallest, while the contact bonding pads and bumps in a region which is farthest to the central point are the biggest. Therefore the situation that the bumps at the edge are liable to peel off may improved.

Abstract: The present invention provides a multi-die semiconductor package structure and a manufacturing method thereof, which includes providing at least two dies and a lead frame including a die pad and a lead wire located at the periphery of the die pad, the die pad has a via hole at the edge thereof, binding a base opposite side of a first die to the die pad; electrically connecting the first die to the lead wire through the via hole; binding a base side of a second die to the die pad, the first and second dies are disposed on the opposite sides of the die pad respectively; electrically connecting the second die to the lead wire; stacking other dies above the first or second die and electrically connecting them to the lead wire; and encapsulating said at least two dies and the lead frame to form a package.

Abstract: A fluxless reflow process for bump formation is provided, which includes: a purifying process for keeping solder in a state of melting or half-melting for 40 s to 540 s; a ball-forming process for melting the solder completely to form ball-like bumps; and a cooling process. The splashing of solder can be avoided and the defect that there may be solder balls around the bumps can be eliminated.

Abstract: Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least over the exposed portion of the metal pad. A second film is deposited over the first film. A photoresist layer is deposited over the substrate, and a trench is formed in the photoresist layer directly over the portion of the metal pad. A first layer is electroplated in the trench over the second film, and a barrier layer is electroplated in trench over the first layer. A termination electrode, comprising tin, is electroplated in the trench over the barrier layer. The photoresist layer is removed. In addition, the method can include etching to remove the second film and first film beyond a predetermined area. The termination electrode is then reflowed.

Abstract: A lead frame comprises a die pad and leads arranged around the die pad. Through holes are provided in the die pad, and the through holes are located in the peripheries, i.e., margin area of the die pad. The through holes serve to be passed through by the metal wires connected with the leads. By means of the above-described lead frame, the subsequent packaging process of the semiconductor chip; including dual chips and/or multi-chips assembly, is simplified and the effect of the manufacturing process is improved, at the same time, the manufacturing cost is reduced.

Abstract: Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least over the exposed portion of the metal pad. A second film is deposited over the first film. A photoresist layer is deposited over the substrate, and a trench is formed in the photoresist layer directly over the portion of the metal pad. A first layer is electroplated in the trench over the second film, and a barrier layer is electroplated in trench over the first layer. A termination electrode, comprising tin, is electroplated in the trench over the barrier layer. The photoresist layer is removed. In addition, the method can include etching to remove the second film and first film beyond a predetermined area. The termination electrode is then reflowed.

Abstract: Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least over the exposed portion of the metal pad. A second film is deposited over the first film. A photoresist layer is deposited over the substrate, and a trench is formed in the photoresist layer directly over the portion of the metal pad. A first layer is electroplated in the trench over the second film, and a barrier layer is electroplated in trench over the first layer. A termination electrode, comprising tin, is electroplated in the trench over the barrier layer. The photoresist layer is removed. In addition, the method can include etching to remove the second film and first film beyond a predetermined area. The termination electrode is then reflowed.

Abstract: The present invention provides a multi-die semiconductor package structure and a manufacturing method thereof, which includes providing at least two dies and a lead frame including a die pad and a lead wire located at the periphery of the die pad, the die pad has a via hole at the edge thereof, binding a base opposite side of a first die to the die pad; electrically connecting the first die to the lead wire through the via hole; binding a base side of a second die to the die pad, the first and second dies are disposed on the opposite sides of the die pad respectively; electrically connecting the second die to the lead wire; stacking other dies above the first or second die and electrically connecting them to the lead wire; and encapsulating said at least two dies and the lead frame to form a package.

Abstract: A lead frame comprises a die pad and leads arranged around the die pad. Through holes are provided in the die pad, and the through holes are located in the peripheries, i.e., margin area of the die pad. The through holes serve to be passed through by the metal wires connected with the leads. By means of the above-described lead frame, the subsequent packaging process of the semiconductor chip; including dual chips and/or multi-chips assembly, is simplified and the effect of the manufacturing process is improved, at the same time, the manufacturing cost is reduced.

Abstract: A method for fabricating a semiconductor device, comprising the steps of: providing a semiconductor substrate including a core device region and an input/output device region, each of which is formed with a gate dielectric layer and a gate on the gate dielectric layer; performing a first ion implantation in the core device region and the input/output device region of the semiconductor substrate with the gate as a mask; performing a rapid thermal annealing to form low-doped source/drain regions in the semiconductor substrate at both sides of the gate dielectric layers of the core device region and the input/output device region; forming spacers over the sidewalls of the gate dielectric layers and gates of the core device region and the input/output device region; and performing a third ion implantation in the core device region and the input/output device region of the semiconductor substrate with the gate and spacer as a mask to form a heavily doped source/drain region.

Abstract: A fluxless reflow process for bump formation is provided, which includes: a purifying process for keeping solder in a state of melting or half-melting for 40 s to 540 s; a ball-forming process for melting the solder completely to form ball-like bumps; and a cooling process. The splashing of solder can be avoided and the defect that there may be solder balls around the bumps can be eliminated.

Abstract: Techniques for an integrated circuit device with planar bond pads are provided. A metal layer region is formed on a substrate. The integrated circuit device also includes a passivation layer that has an opening formed around the metal layer region. The passivation layer and a top surface of the metal layer region defines a continuous planar surface. An under bump metallurgy structure, sized and positioned to completely overlay the top surface of the metal layer region, is coupled to the continuous planar surface. The under bump metallurgy structure is coupled to a bump termination electrode. Preferably, a top surface of the bump termination electrode has a maximum surface nonuniformity of less than about 1 micron.

Abstract: Techniques for an integrated circuit device with planar bond pads are provided. A metal layer region is formed on a substrate. The integrated circuit device also includes a passivation layer that has an opening formed around the metal layer region. The passivation layer and a top surface of the metal layer region defines a continuous planar surface. An under bump metallurgy structure, sized and positioned to completely overlay the top surface of the metal layer region, is coupled to the continuous planar surface. The under bump metallurgy structure is coupled to a bump termination electrode. Preferably, a top surface of the bump termination electrode has a maximum surface nonuniformity of less than about 1 micron.

Abstract: A method of making an electrical contact bump electrical contact structure on a substrate comprising: providing a substrate having a bond pad, and a passivation layer overlying a portion for the substrate and wherein the passivation layer includes an opening therein exposing a portion of the bond pad, and wherein the passivation layer has a raised portion overlying the bond pad; forming an under bump metallurgy over at least the exposed portion of the bond pad and over at least a portion of the raised portion of the passivation layer overlying the bond pad; forming a sacrificial blanket having an opening therein that in cross-section has an inverted T-shape over the substrate so that the opening in the sacrificial blanket is aligned with the bond pad; and depositing an electrically conductive material into the opening in the sacrificial blanket.

Abstract: A method of making an electrical contact bump electrical contact structure on a substrate comprising: providing a substrate having a bond pad, and a passivation layer overlying a portion of the substrate and wherein the passivation layer includes an opening therein exposing a portion of the bond pad, and wherein the passivation layer has a raised portion overlying the bond pad; forming an under bump metallurgy over at least the exposed portion of the bond pad and over at least a portion of the raised portion of the passivation layer overlying the bond pad; forming a sacrificial blanket having an opening therein that in cross-section has an inverted T-shape over the substrate so that the opening in the sacrificial blanket is aligned with the bond pad; and depositing an electrically conductive material into the opening in the sacrificial blanket.

Abstract: A semiconductor die package design incorporating at least a pair of functional semiconductor dies. The input/output pads locations on one of the dies (the daughter die) are located at the near mirror image of the original die (mother die). The package architecture includes two dies back-to-back or stacked dies back-to-back, therefore a plurality of input/output interconnections can be formed. The package increases density and performance by twofold or more compared to a regular package containing only one die with the same footprint. At least one additional pin can be dedicated as the chip select pin for the daughter die or multiple dies. The other pins can be shared with the mother die.