Abstract: This invention discloses a trigger circuit for an electrostatic discharge (ESD) protection device, the ESD protection device being turned on during an ESD event and being turned off during a normal operation, the trigger circuit comprises a voltage sensing circuit coupled to a bonding pad, the voltage sensing circuit being configured to produce a first predetermined voltage during a ESD event, and to produce a second predetermined voltage complimentary to the first predetermined voltage during a normal operation, and a voltage converting circuit having a positive feedback circuit and coupled between the voltage sensing circuit and the ESD protection device for converting the first predetermined voltage to a third predetermined voltage for turning on the ESD protection device, and for converting the second predetermined voltage to a fourth predetermined voltage for turning off the ESD protection device.

Abstract: This invention discloses a trigger circuit for an electrostatic discharge (ESD) protection device, the ESD protection device being turned on during an ESD event and being turned off during a normal operation, the trigger circuit comprises a voltage sensing circuit coupled to a bonding pad, the voltage sensing circuit being configured to produce a first predetermined voltage during a ESD event, and to produce a second predetermined voltage complimentary to the first predetermined voltage during a normal operation, and a voltage converting circuit having a positive feedback circuit and coupled between the voltage sensing circuit and the ESD protection device for converting the first predetermined voltage to a third predetermined voltage for turning on the ESD protection device, and for converting the second predetermined voltage to a fourth predetermined voltage for turning off the ESD protection device.

Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

Abstract: A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

Abstract: A structure of a 2-bit mask ROM device and a fabrication method thereof are provided. The memory structure includes a substrate, a gate structure, a 2-bit coding implantation region, a spacer, a buried drain region, an isolation structure and a word line. The gate structure is disposed on the substrate, while the coding implantation region is located in the substrate under the side of the gate structure. Further, at least one spacer is arranged beside the side of the gate structure and a buried drain region is disposed in the substrate beside the side of the spacer. Moreover, the buried drain region and the coding implantation region further comprise a buffer region in between. Additionally, an insulation structure is arranged on the substrate that is above the buried drain region, while the word lien is disposed on the gate structure.

Abstract: To reduce the disturbance between adjacent memory cells, an improved ONO flash memory array is implanted with a pocket on one side of the channel of each memory cell or two pockets of different concentrations on both sides of the channel, thereby resulting in memory cells with asymmetric pockets. Consequently, no disturbances occurred between adjacent memory cells when the ONO flash memory array is programmed or erased by band-to-band techniques, and the disturbances between adjacent memory cells are also suppressed during reading process.

Abstract: A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

Abstract: To reduce the disturbance between adjacent memory cells, an improved ONO flash memory array is implanted with a pocket on one side of the channel of each memory cell or two pockets of different concentrations on both sides of the channel, thereby resulting in memory cells with asymmetric pockets. Consequently, no disturbances occurred between adjacent memory cells when the ONO flash memory array is programmed or erased by band-to-band techniques, and the disturbances between adjacent memory cells are also suppressed during reading process.

Abstract: A method of manufacturing chalcogenide memory in a semiconductor substrate.

Abstract: A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

Abstract: A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

Abstract: A trim circuit and method for tuning a current level of a reference cell in a flash memory that includes a sense amplifier to compare a cell current from a memory cell whose gate receives a word line signal voltage with a reference current from the reference cell whose gate receives a bias voltage produced by dividing the word line signal voltage by a voltage divider to thereby produce a sense signal. The voltage divider includes at least a programmable flash cell to serve as a variable resistor whose resistance is determined by programming the programmable flash cell by a programming/erasing circuit in reference to the programming of the memory cell.

Abstract: A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is disposed on the substrate. The double diffused source/drain region is positioned beside the sides of the gate in the substrate, wherein the second doped region is located at the periphery of the first doped region in the substrate. The channel region is located between the double diffused source/drain region in the substrate. The coding region is disposed in the substrate at the intersection between the sides of the channel region and the double diffused source/drain region. The dielectric layer is disposed above the double diffused source/drain region, while the word line is disposed above the dielectric layer and the gate.

Abstract: A fabrication method for a flash memory device with a split floating gate is described. The method provides a substrate, wherein an oxide layer and a patterned sacrificial layer are sequentially formed on the substrate. Ion implantation is then conducted to form source/drain regions with lightly doped source/drain regions in the substrate beside the sides of the patterned sacrificial layer using the patterned sacrificial layer as a mask. Isotropic etching is further conducted to remove a part of the patterned sacrificial layer, followed by forming two conductive spacers on the sidewalls of the patterned sacrificial layer. The patterned sacrificial layer and oxide layer that is exposed by the two conductive spacers are then removed to form two floating gates. Subsequently, a dielectric layer and a control gate are formed on the substrate.

Abstract: A method for fabricating a non-volatile memory is described. A substrate having a strip stacked structure thereon is provided. A buried drain is then formed in the substrate beside the strip stacked structure and an insulating layer is formed on the buried drain. A silicon layer and a cap layer are sequentially formed over the substrate. The cap layer, the silicon layer and the strip stacked structure are then patterned successively in a direction perpendicular to the buried drain, wherein the strip stacked structure is patterned into a plurality of gates. A liner oxide layer is formed on the exposed surfaces of the gates, the substrate and the silicon layer. Thereafter, the cap layer is removed and a metal salicide layer is formed on the exposed surface of the silicon layer.

Abstract: A reference current generation circuit for the multiple bit flash memory provided by the present invention applies the same boosted word-line voltage to the gates of different reference current generation unit's reference cells, and uses different gate lengths from different reference cells to obtain the reference currents with different levels that are needed. Therefore, it effectively solves the problem of the reference currents having different drifts along with the variance of the temperature and the power voltage Vcc.

Abstract: The reference current generation circuit of a multiple bit flash memory. An identical boosted word-line voltage is applied to the gate terminal of reference memory cells in different reference current generation units and a different substrate voltage is applied to the substrate of each reference memory cell so that different reference currents are produced. This arrangement reduces different degree of shifting in the reference currents due to temperature and source voltage Vcc variation.