Abstract: A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

Abstract: A NROM cell for reducing for reducing the second-bit effect is described. The NORM cell of the present invention is formed with a substrate, a silicon oxide/silicon nitride/silicon oxide (ONO) layer disposed on the substrate, a gate disposed on the silicon oxide/silicon nitride/silicon oxide layer, source/drain regions configured in the substrate beside the gate, and a shallow pocket doped region configured between the source/drain regions and the ONO layer beside the gate. The depth of the shallow pocket doped region is sufficiently small to prevent interference to the current flow that travels to the source/drain regions.

Abstract: A structure of a 2-bit mask ROM device and a fabrication method thereof are provided. The memory structure includes a substrate, a gate structure, a 2-bit coding implantation region, a spacer, a buried drain region, an isolation structure and a word line. The gate structure is disposed on the substrate, while the coding implantation region is located in the substrate under the side of the gate structure. Further, at least one spacer is arranged beside the side of the gate structure and a buried drain region is disposed in the substrate beside the side of the spacer. Moreover, the buried drain region and the coding implantation region further comprise a buffer region in between. Additionally, an insulation structure is arranged on the substrate that is above the buried drain region, while the word lien is disposed on the gate structure.

Abstract: A reference current generation circuit for the multiple bit flash memory provided by the present invention applies the same boosted word-line voltage to a voltage dividing circuit of the different reference current generation unit, so as to generate a gate voltage for the different reference current generation unit's reference cell to obtain the reference currents with different levels that are needed. Therefore, it effectively solves the problem of the reference currents having different drifts along with the variance of the temperature and the power voltage Vcc.

Abstract: A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is disposed on the substrate. The double diffused source/drain region is positioned beside the sides of the gate in the substrate, wherein the second doped region is located at the periphery of the first doped region in the substrate. The channel region is located between the double diffused source/drain region in the substrate. The coding region is disposed in the substrate at the intersection between the sides of the channel region and the double diffused source/drain region. The dielectric layer is disposed above the double diffused source/drain region, while the word line is disposed above the dielectric layer and the gate.

Abstract: Disclosed is a trim circuit and method for tuning a current level of a reference cell in a flash memory that includes a sense amplifier to compare a cell current from a memory cell whose gate receives a word line signal voltage with a reference current from the reference cell whose gate receives a bias voltage produced by dividing the word line signal voltage by a voltage divider to thereby produce a sense signal. The voltage divider includes at least a programmable flash cell to serve as a variable resistor whose resistance is determined by programming the programmable flash cell by a programming/erasing circuit in reference to the programming of the memory cell.

Abstract: A device for converging an erased flash memory array. The memory array includes a plurality of memory cells, each memory cell having a control gate, a floating gate, a source, and a drain. The drain voltage supply is coupled to the drain for providing a positive drain voltage. The constant current supply is coupled to the source for providing a source current. The control gate power supply is coupled to the control gate for providing a gradually increasing gate voltage to the control gate to control the source current flowing through the memory cell and adjust the threshold voltage of the memory cells.

Abstract: A method of manufacturing chalcogenide memory in a semiconductor substrate.

Abstract: A method is used for testing a tunneling oxide layer of a flash memory. The method includes providing a test device. The test device includes a diffusion region, a floating gate electrode above the diffusion region, and a tunneling oxide layer disposed between the diffusion region and the floating gate electrode. Multiple contacts are disposed over the periphery of the floating gate but not over the diffusion region. Multiple contacts are disposed over the diffusion region. A first voltage is applied to the floating-gate contacts and A second voltage is applied on to the diffusion-region contacts.

Abstract: The present invention relates to a method for fabricating a nitride read only memory (NROM), comprising: forming a doped polysilicon layer over a substrate, defining the doped polysilicon layer by using a patterned mask layer to form a plurality of doped polysilicon lines and expose a portion of the substrate. Afterwards, a thermal process is performed to form an oxide layer on the exposed substrate and sidewalls of the doped polysilicon lines. During the thermal process, the dopants are driven into the substrate to form a source/drain region, thus obtaining a plurality of bit lines including the doped polysilicon lines and the source/drain region. Following removal of the patterned mask layer, a self-aligned silicide layer is formed on the top surface of the bit lines. After removing the oxide layer, a silicon nitride stacked layer and a plurality of word lines are formed over the substrate.

Abstract: A flash memory with virtual ground scheme. The memory includes a first type substrate, second type doped regions, a stacked gate structure, a first type ion-implanted region, and switches. The second type doped regions are formed in the first type substrate. The stacked gate structure is formed on the surface of the first type substrate and between the second type doped regions. The first type ion-implanted region is formed on only one side of the second type doped region and the first type substrate. The switches are coupled to the second type doped regions respectively for selective provision of a predetermined voltage value and a ground level to the second type doped regions.

Abstract: A fabrication method for a high voltage device is described. A substrate is provided, wherein a gate structure of a high voltage device is already formed on the substrate. Thereafter, a first thermal process is conducted to form a first doped region in the substrate beside the gate structure of the high voltage device. A spacer is formed on the side of the gate structure of the high voltage device. An oxide layer is further formed on the gate structure of the high voltage device and on the surface of the first doped region. After this, a second thermal process is performed to form a second doped region in the substrate beside the side of the spacer.

Abstract: A method for fabricating a non-volatile memory is described. A substrate having a strip stacked structure thereon is provided. A buried drain is then formed in the substrate beside the strip stacked structure and an insulating layer is formed on the buried drain. A silicon layer and a cap layer are sequentially formed over the substrate. The cap layer, the silicon layer and the strip stacked structure are then patterned successively in a direction perpendicular to the buried drain, wherein the strip stacked structure is patterned into a plurality of gates. A liner oxide layer is formed on the exposed surfaces of the gates, the substrate and the silicon layer. Thereafter, the cap layer is removed and a metal salicide layer is formed on the exposed surface of the silicon layer.

Abstract: A method is used for testing a tunneling oxide layer of a flash memory. The method includes providing a test device. The test device includes a diffusion region, a floating gate electrode above the diffusion region, and a tunneling oxide layer disposed between the diffusion region and the floating gate electrode. Multiple contacts are disposed over the periphery of the floating gate but not over the diffusion region. Multiple contacts are disposed over the diffusion region. A first voltage is applied to the floating-gate contacts and A second voltage is applied on to the diffusion-region contacts.

Abstract: A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

Abstract: A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate structure; at least one spacer, disposed on both sides of the gate structure; a buried drain region, configured in the substrate beside both sides of the spacer; a doped region, configured in the substrate between the buried drain region and the 2-bit code region, wherein the dopant type of the doped region is different from that for the 2-bit code region and the dopant concentration in the doped region is higher than that in the 2-bit code region; an insulation layer, disposed above the buried drain region; and a word line disposed on the gate structures along a same row.

Abstract: A Mask ROM testing device is described. The Mask ROM testing device comprises a substrate, a plurality of buried bit-lines in the substrate and a plurality of word-lines on the substrate perpendicular to the buried bit-lines. Each buried bit-line has two end portions with a combined length of about 3˜30 &mgr;m and can have an N-type conductivity or a P-type conductivity.

Abstract: A method for manufacturing a semiconductor device. A trench is formed in a substrate. An insulation spacer is then formed on the sidewall of the trench. A first epitaxial silicon layer is formed in the trench, followed by doping the first epitaxial layer as a doped source/drain (S/D) region. A second epitaxial silicon layer is formed on the substrate and on the first epitaxial silicon layer, followed by forming a gate on the second epitaxial silicon layer. Then using the gate as a mask, ions are implanted to form an extended doped region. Thereafter, a rapid thermal annealing is performed to convert both the source/drain doped region and the extended doped region to a source/drain region.

Abstract: A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

Abstract: A non-volatile semiconductor memory device with a multi-layer gate insulating structure is provided. The non-volatile semiconductor memory device comprises a gate insulating structure formed between a gate and a channel region, which includes a top silicon nitride layer, an intermediate silicon nitride layer and a bottom silicon nitride layer. When an electric field is applied between the gate and a drain region beside the channel region, hot carriers exhibit a direct tunneling across the bottom silicon nitride layer from the drain region for a write-erase operation. The hot carriers having exhibited the direct tunneling from the drain region are trapped into the intermediate silicon nitride layer.